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FPGA 后仿真端口问题，输入Clk,Rst_n,a。输出b,c。前仿真没问题，后仿真出现问题不知道什么原因。
module dpram(
Clk,
Rst_n,
a,
b,
c
);
input Clk;
input Rst_n;
input a;
output reg b;
output reg c;
always@(posedge Clk)
if(!Rst_n) begin
b <= 1'b0;
c <= 1'b0;
end
else begin
b <= a;
c <= b;
end
endmodule
`timescale 1ns/1ns
`define clk_period 20
module dpram_tb();
reg Clk;
reg Rst_n;
reg a;
wire b;
wire c;
dpram dpram(
.Clk(Clk),
.Rst_n(Rst_n),
.a(a),
.b(b),
.c(c)
);
initial Clk = 1;
always#(`clk_period/2)Clk = ~Clk;
initial begin
Rst_n = 0;
a = 1'b0;
#(`clk_period*2);
Rst_n = 1;
#(`clk_period*2);
repeat(20)begin
a = 1'b1;
#(`clk_period);
a = 1'b0;
#(`clk_period);
end
$stop;
end
endmodule
** Error: (vsim-3389) C:/Users/lipen/Desktop/dpram/prj/../testbench/dpram_tb.v(21): Port 'c' not found in the connected module (5th connection).
#
# Region: /dpram_tb/dpram
# ** Fatal: (vsim-3365) C:/Users/lipen/Desktop/dpram/prj/../testbench/dpram_tb.v(21): Too many port connections. Expected 4, found 5.
# Time: 0 ps Iteration: 0 Instance: /dpram_tb/dpram File: dpram_8_1200mv_85c_slow.vo
# FATAL ERROR while loading design
# Error loading design
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发表于 2024-8-28 21:39:09