【Vivado常见问题】【DRC NSTD-1 DRC UCIO-1】无法生成bitstream（部分管脚位置或电平未指定）

admin

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To
allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a, b, out, and sel.


[DRC UCIO-1] Unconstrained Logical Port: 4 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: a, b, out, and sel.



问题原因

此种情况发生在对一个工程进行全编译后生成bitstream时，如果没有给工程添加IO约束，那么整个工程生成的bitstream就没有任何意义，所以生成bitstream的时候就会报该错误并生成失败。


正确的做法

仔细检查管脚，看是否报告的对应管脚没有指定位置，电平，然后根据实际物理电路给工程加入合理且正确的IO约束之后，再编译生成bitstream。


例外情况

但是假如工程就是有些信号暂时没法指定管脚呢，比如顶层设计端口包含串口，LED、按键，此时只想验证按键和串口，LED由于当前硬件限制没有对应的物理电路，没法确定管脚。这种情况可以使用一句脚本语言来暂时忽略该限制。只需要创建一个tcl脚本，在脚本中输入下述内容即可
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

，然后在工程设置中的Bitstream选项中，添加该tcl文件到tcl.pre项中，如下图所示：





以下为编写好的tcl文件。
pre_hook.tcl (171 Bytes, 下载次数: 700)

2020-10-24 13:13 上传

点击文件名下载附件

或者不创建文件，直接将上面三句话写在你工程的管脚约束xdc文件的开头也是可以的。