解决方案原文链接:https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/embedded/2018/unable-to-make-preloader-in-windows-10.html
报错信息如下图所示:
Unable to make preloader in Windows 10
Description
This issue comes when using SOC EDS tool to generate the preloader. After creating the new HPS and BSP settings file, make command is giving a failure: tar zxf /cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz tar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz' make: *** [uboot-socfpga/.untar] Error 1
该故障在使用SoC EDS生成preloader的时候出现。当创建了新的HPS和BSP设置文件,make命令会报如下失败: tar zxf /cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz tar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz' make: *** [uboot-socfpga/.untar] Error 1
Workaround/Fix 维修方法:
原文:In order to workaround this issue, two files need to be modifed before executing the make command. 译文:为了维修该故障,在make命令之前需要修改两个文件。 原文:1. C:\<installation_directory>\embedded\ip\altera\preloader\src\Makefile.template 译文:1、C:\<installation_directory>\embedded\ip\altera\preloader\src\Makefile.template文件 原文:Change the current file with the attached one in this link (make sure to unzip file before you copy) 译文:使用本帖子附件中的文件中的对应文件替换该“Makefile.template”文件
原文:2. C:\<installation_directory>\embedded\host_tools\cygwin\etc\fstabin in fstab file:comment this line: 译文:在fstab文件中,注释掉如下行内容 - #none /cygdrive cygdrive binary,posix=0,user 0 0
复制代码原文:and add this line instead: 译文:并添加如下行内容以作为替换: - none /cygdrive cygdrive binary,posix=0,user,noacl 0 0
复制代码
原文:This issue is scheduled to be fixed in future release of Intel® Quartus Prime software. 译文:该故障会在未来的新版本软件中修复。
特别注意:修改完成之后需要删除工程目录下的software文件夹中的“spl_bsp”文件夹后重新通过bsp-editor生成bsp文件再编译,否则还是会继续报错。
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