【07.17已解决】DAC实验测试电压异常

Deer-菜籽 · 发表于 2018-7-17 10:06:41

本帖最后由 Deer-菜籽于 2018-7-17 15:19 编辑

在DAC实验里
modelsim仿真波形正常
捕获.JPG

但实际电压表测试电压均为0V
期间怀疑过DAC芯片但出产固件测试DB引脚电压正常增长
故可以排除DAC芯片问题应该是驱动当中出了什么问题

ISSP设置如下
捕获2.JPG

实在找不出来问题出在哪里
后附上各文件代码

DAC_top

module DAC_top(
clk,
rst_n,
key,
DIN,
CS_N,
SCLK
);
input clk,rst_n;
input key;
output wire DIN;
output wire CS_N;
output wire SCLK;
wire [15:0] DAC_DATA;
wire DAC_STATE;
reg START;
DAC_driver DAC_driver(
.clk (clk),
.rst_n (rst_n),
.START (START),
.DAC_DATA (DAC_DATA),
.CS_N (CS_N),
.SCLK (SCLK),
.DIN (DIN),
.DAC_STATE (DAC_STATE)
);
DAC DAC_test (
.probe (DAC_DATA[11:0]), // probes.probe
.source (DAC_DATA) // sources.source
);
reg [15:0] DAC_DATA_r;
always@ (posedge clk or negedge rst_n)
if(!rst_n)
DAC_DATA_r <= 16'd0;
else if (DAC_STATE)
DAC_DATA_r <= DAC_DATA;
else
DAC_DATA_r <= DAC_DATA_r;
always@ (posedge clk or negedge rst_n)
if(!rst_n)
START <= 1'b0;
else if (DAC_DATA_r != DAC_DATA)
START <= 1'b1;
else
START <= 1'b0;
endmodule

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DAC_driver

`define DIV_PARAM 2
module DAC_driver(
clk,
rst_n,
START,
DAC_DATA,
CS_N,
SCLK,
DIN,
DAC_STATE
);
input clk,rst_n;
input START;
input [15:0] DAC_DATA;
output reg CS_N;
output reg SCLK;
output reg DIN;
output DAC_STATE;
/* 处理 START 信号 */
/* 当出现 START 信号时，work = 1 表示正在工作不接受触发
当出现 conv_finish 信号时，work = 0 表示不在工作可以被触发 */
reg work;
reg conv_finish;
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
work <= 1'b0;
else if ( conv_finish )
work <= 1'b0;
else if (START)
work <= 1'b1;
else
work <= work;
end
/* SCLK2X 时钟产生 */
/* 数据手册显示 TLV5618 最大时钟频率20MHz
所以取SCLK2X 频率为25MHz 即进行2分频
如此 SCLK 即为 12.5 MHz 符合器件要求 */
reg [7:0] cnt_SCLK2X;
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
cnt_SCLK2X <= 8'd0;
else if (work) begin
if (cnt_SCLK2X == ( (`DIV_PARAM) - 1'b1 ) )
cnt_SCLK2X <= 8'd0;
else
cnt_SCLK2X <= cnt_SCLK2X + 1'b1;
end
else
cnt_SCLK2X <= 8'd0;
end
reg SCLK2X;
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
SCLK2X <= 1'b0;
else if ( work && ( cnt_SCLK2X == ( (`DIV_PARAM) - 1'b1 ) ) )
SCLK2X <= 1'b1;
else
SCLK2X <= 1'b0;
end
/* 线性序列计数器 */
reg [5:0]cnt_LSM;
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
cnt_LSM <= 6'd0;
else if ( work && SCLK2X ) begin
if ( cnt_LSM == 6'd33 )
cnt_LSM <= 6'd0;
else if (SCLK2X)
cnt_LSM <= cnt_LSM + 1'b1;
end
else
cnt_LSM <= cnt_LSM ;
end
/* 线性序列机 */
reg [15:0] DAC_DATA_r;
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
DAC_DATA_r <= 16'd0;
else if (work)
DAC_DATA_r <= DAC_DATA;
else
DAC_DATA_r <= DAC_DATA;
end
always@ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
CS_N <= 1'b1;
DIN <= 1'b1;
SCLK <= 1'b1;
end
else if (work) begin
if (SCLK2X) begin
case (cnt_LSM)
0: begin SCLK <= 1'b0; CS_N <= 1'b0; end
1: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[15]; end
3: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[14]; end
5: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[13]; end
7: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[12]; end
9: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[11]; end
11: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[10]; end
13: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 9]; end
15: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 8]; end
17: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 7]; end
19: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 6]; end
21: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 5]; end
23: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 4]; end
25: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 3]; end
27: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 2]; end
29: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 1]; end
31: begin SCLK <= 1'b1; DIN <= DAC_DATA_r[ 0]; end
2,4,6,8,10,12,14,16,18,20,22,24,26,28,30:
begin SCLK <= 1'b0; end
32: begin SCLK <= 1'b1; end
33: begin CS_N <= 1'b1; end
default : begin CS_N <= 1'b1; DIN <= 1'b1; SCLK <= 1'b1; end
endcase
end
else ;
end
else CS_N <= 1'b1;
end
/* 当数据转换完成时候输出一个 conv_finish 信号脉冲 */
always@ (posedge clk or negedge rst_n) begin
if(!rst_n)
conv_finish <= 1'b0;
else if ( work && SCLK2X && (cnt_LSM == 6'd33) )
conv_finish <= 1'd1;
else
conv_finish <= 1'b0;
end
assign DAC_STATE = work;
endmodule

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DAC_tb

`timescale 1ns/1ns
`define timeperiod 20
module DAC_tb();
reg clk,rst_n;
reg START;
reg [15:0] DAC_DATA;
wire CS_N;
wire SCLK;
wire DIN;
wire DAC_STATE;
DAC_driver DAC_driver(
.clk (clk),
.rst_n (rst_n),
.START (START),
.DAC_DATA (DAC_DATA),
.CS_N (CS_N),
.SCLK (SCLK),
.DIN (DIN),
.DAC_STATE (DAC_STATE)
);
initial clk = 1'b0;
always #(`timeperiod / 2) clk = ~clk;
initial begin
rst_n = 1'b0;
#(`timeperiod * 10);
rst_n = 1'b1;
#(`timeperiod * 20);
DAC_DATA = 16'hC_AAA;
START = 1;
#20;
START = 0;
#200;
wait(!DAC_STATE);
#2000;
DAC_DATA = 16'h4_555;
START = 1;
#20;
START = 0;
#200;
wait(!DAC_STATE);
#2000;
#2000;
$stop;
end
endmodule

复制代码

DAC_TLV5618.zip (3.98 KB, 下载次数: 492)

Deer-菜籽 · 发表于 2018-7-17 15:17:14

找到了找到了
加上昨天几乎是整整一天...
线性序列机里面写错了
之前改着改着改懵了

Deer-菜籽 · 发表于 2018-7-17 11:05:41

另外还有一个问题 ISSP在Source 端输入数据的时候可以自定义数据类型吗
应该在哪里设置呢

Deer-菜籽 · 发表于 2018-7-17 12:40:24

本帖最后由 fzwwj95 于 2018-7-17 21:09 编辑

Deer-菜籽发表于 2018-7-17 11:05
另外还有一个问题 ISSP在Source 端输入数据的时候可以自定义数据类型吗
应该在哪里设置呢 ...

谢谢袁玉卓
ISSP的数据定义部分找到了
不过驱动部分的问题还没找到下午再继续啦

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