这个vhdl程序运行不出来结果是怎么回事

兰因絮果.

我查了说是时钟对那个逻辑不起作用，但是怎么改啊
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lk_lc is
port(CLK,LP,LR,cnt_1,cnt_2,cnt_3:in std_logic;
      LEDLut std_logic_vector(2 downto 0));
end;
architecture behave of lk_lc is
signal cnt:std_logic_vector(24 downto 0);
signal cnt_1 : std_logic;
signal cnt_2 : std_logic;
signal cnt_set : std_logic;
begin
process(CLK,LP,LR)
variable count : integer range 0 to 2 := 0;
begin
if LP = '0' then  
LEDL<= (others=>'0');
count := 0;
   elsif CLK'event and CLK='1' then
    if cnt_set = '1' then  
  case count is   
      when 0 =>     LEDL <= "001";   
    when 1 =>     LEDL <= "010";   
    when 2 =>      LEDL <= "100";   
    when others=>     null;  
  end case;     
  if count = 2 then   
          count := 0;   
    else    count := count + 1;   
     end if;   
   end if;
end if;
end process;
process(LP,clk)
begin
if LP = '0' then  
  cnt <= (others=>'0');  
  cnt_1 <= '0';  cnt_2 <= '0';  cnt_set <= '0';
  elsif clk'event and clk = '1' then  
     if cnt_2 = '0' and cnt_1 = '1' and cnt(23)='1' then  
      cnt_set <= '1';  
   else   cnt_set <= '0';
   end if;  
   cnt <= cnt + 1;  cnt_2 <= cnt_1;  cnt_1 <= cnt(23);
end if;
end process;
end behave;