Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\gao_project\41_ov5640x2_udp_rgmii\ov5640x2_udp_rgmii\src\eth_dcfifo\temp\FIFO\fifo_define.v
H:\01_gaoyun\gao_project\41_ov5640x2_udp_rgmii\ov5640x2_udp_rgmii\src\eth_dcfifo\temp\FIFO\fifo_parameter.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\edc.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-2
Part Number GW5A-LV25UG324ES
Device GW5A-25
Created Time Wed Jul 19 17:44:10 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module eth_dcfifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.453s, Peak memory usage = 38.672MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.672MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.672MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.672MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 38.672MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.672MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.672MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.672MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.672MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 38.672MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.672MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.672MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.554s, Peak memory usage = 44.176MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.176MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.176MB
Total Time and Memory Usage CPU time = 0h 0m 0.981s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.176MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 49
I/O Buf 49
    IBUF 13
    OBUF 36
Register 111
    DFFPE 5
    DFFCE 106
LUT 122
    LUT2 21
    LUT3 46
    LUT4 55
ALU 39
    ALU 39
SSRAM 4
    RAM16S4 4
INV 4
    INV 4
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 189(126 LUTs, 39 ALUs, 4 SSRAMs) / 23040 <1%
Register 111 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 111 / 23685 <1%
BSRAM 2 / 56 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I
fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n4_s2/O
fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n9_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.0(MHz) 167.9(MHz) 9 TOP
2 WrClk 100.0(MHz) 176.7(MHz) 9 TOP
3 fifo_inst/n4_6 100.0(MHz) 1984.1(MHz) 1 TOP
4 fifo_inst/n9_6 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.045
Data Arrival Time 6.783
Data Required Time 10.828
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_12_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 49 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 10 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[3]
2.086 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_10_s0/I1
2.641 0.555 tINS FF 3 fifo_inst/Equal.wcount_r_10_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_8_s0/I0
3.395 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_8_s0/F
3.632 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.148 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_2_s0/F
4.385 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
5.865 0.035 tINS FF 1 fifo_inst/rcnt_sub_5_s/COUT
5.865 0.000 tNET FF 2 fifo_inst/rcnt_sub_6_s/CIN
5.900 0.035 tINS FF 1 fifo_inst/rcnt_sub_6_s/COUT
5.900 0.000 tNET FF 2 fifo_inst/rcnt_sub_7_s/CIN
5.935 0.035 tINS FF 1 fifo_inst/rcnt_sub_7_s/COUT
5.935 0.000 tNET FF 2 fifo_inst/rcnt_sub_8_s/CIN
5.970 0.035 tINS FF 1 fifo_inst/rcnt_sub_8_s/COUT
5.970 0.000 tNET FF 2 fifo_inst/rcnt_sub_9_s/CIN
6.005 0.035 tINS FF 1 fifo_inst/rcnt_sub_9_s/COUT
6.005 0.000 tNET FF 2 fifo_inst/rcnt_sub_10_s/CIN
6.041 0.035 tINS FF 1 fifo_inst/rcnt_sub_10_s/COUT
6.041 0.000 tNET FF 2 fifo_inst/rcnt_sub_11_s/CIN
6.076 0.035 tINS FF 1 fifo_inst/rcnt_sub_11_s/COUT
6.076 0.000 tNET FF 1 fifo_inst/rcnt_sub_12_s/CIN
6.546 0.470 tINS FF 1 fifo_inst/rcnt_sub_12_s/SUM
6.783 0.237 tNET FF 1 fifo_inst/Rnum_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 49 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_12_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Rnum_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.029, 68.058%; route: 1.659, 28.023%; tC2Q: 0.232, 3.919%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.080
Data Arrival Time 6.748
Data Required Time 10.828
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_11_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 49 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 10 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[3]
2.086 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_10_s0/I1
2.641 0.555 tINS FF 3 fifo_inst/Equal.wcount_r_10_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_8_s0/I0
3.395 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_8_s0/F
3.632 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.148 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_2_s0/F
4.385 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
5.865 0.035 tINS FF 1 fifo_inst/rcnt_sub_5_s/COUT
5.865 0.000 tNET FF 2 fifo_inst/rcnt_sub_6_s/CIN
5.900 0.035 tINS FF 1 fifo_inst/rcnt_sub_6_s/COUT
5.900 0.000 tNET FF 2 fifo_inst/rcnt_sub_7_s/CIN
5.935 0.035 tINS FF 1 fifo_inst/rcnt_sub_7_s/COUT
5.935 0.000 tNET FF 2 fifo_inst/rcnt_sub_8_s/CIN
5.970 0.035 tINS FF 1 fifo_inst/rcnt_sub_8_s/COUT
5.970 0.000 tNET FF 2 fifo_inst/rcnt_sub_9_s/CIN
6.005 0.035 tINS FF 1 fifo_inst/rcnt_sub_9_s/COUT
6.005 0.000 tNET FF 2 fifo_inst/rcnt_sub_10_s/CIN
6.041 0.035 tINS FF 1 fifo_inst/rcnt_sub_10_s/COUT
6.041 0.000 tNET FF 2 fifo_inst/rcnt_sub_11_s/CIN
6.511 0.470 tINS FF 1 fifo_inst/rcnt_sub_11_s/SUM
6.748 0.237 tNET FF 1 fifo_inst/Rnum_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 49 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_11_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Rnum_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.994, 67.868%; route: 1.659, 28.190%; tC2Q: 0.232, 3.942%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.115
Data Arrival Time 6.712
Data Required Time 10.828
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_10_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 49 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 10 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[3]
2.086 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_10_s0/I1
2.641 0.555 tINS FF 3 fifo_inst/Equal.wcount_r_10_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_8_s0/I0
3.395 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_8_s0/F
3.632 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.148 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_2_s0/F
4.385 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
5.865 0.035 tINS FF 1 fifo_inst/rcnt_sub_5_s/COUT
5.865 0.000 tNET FF 2 fifo_inst/rcnt_sub_6_s/CIN
5.900 0.035 tINS FF 1 fifo_inst/rcnt_sub_6_s/COUT
5.900 0.000 tNET FF 2 fifo_inst/rcnt_sub_7_s/CIN
5.935 0.035 tINS FF 1 fifo_inst/rcnt_sub_7_s/COUT
5.935 0.000 tNET FF 2 fifo_inst/rcnt_sub_8_s/CIN
5.970 0.035 tINS FF 1 fifo_inst/rcnt_sub_8_s/COUT
5.970 0.000 tNET FF 2 fifo_inst/rcnt_sub_9_s/CIN
6.005 0.035 tINS FF 1 fifo_inst/rcnt_sub_9_s/COUT
6.005 0.000 tNET FF 2 fifo_inst/rcnt_sub_10_s/CIN
6.475 0.470 tINS FF 1 fifo_inst/rcnt_sub_10_s/SUM
6.712 0.237 tNET FF 1 fifo_inst/Rnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 49 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_10_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Rnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.959, 67.674%; route: 1.659, 28.360%; tC2Q: 0.232, 3.966%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.150
Data Arrival Time 6.677
Data Required Time 10.828
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_9_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 49 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 10 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[3]
2.086 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_10_s0/I1
2.641 0.555 tINS FF 3 fifo_inst/Equal.wcount_r_10_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_8_s0/I0
3.395 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_8_s0/F
3.632 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.148 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_2_s0/F
4.385 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
5.865 0.035 tINS FF 1 fifo_inst/rcnt_sub_5_s/COUT
5.865 0.000 tNET FF 2 fifo_inst/rcnt_sub_6_s/CIN
5.900 0.035 tINS FF 1 fifo_inst/rcnt_sub_6_s/COUT
5.900 0.000 tNET FF 2 fifo_inst/rcnt_sub_7_s/CIN
5.935 0.035 tINS FF 1 fifo_inst/rcnt_sub_7_s/COUT
5.935 0.000 tNET FF 2 fifo_inst/rcnt_sub_8_s/CIN
5.970 0.035 tINS FF 1 fifo_inst/rcnt_sub_8_s/COUT
5.970 0.000 tNET FF 2 fifo_inst/rcnt_sub_9_s/CIN
6.440 0.470 tINS FF 1 fifo_inst/rcnt_sub_9_s/SUM
6.677 0.237 tNET FF 1 fifo_inst/Rnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 49 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_9_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Rnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.924, 67.478%; route: 1.659, 28.532%; tC2Q: 0.232, 3.990%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.186
Data Arrival Time 6.642
Data Required Time 10.828
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_8_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 49 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 10 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[3]
2.086 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_10_s0/I1
2.641 0.555 tINS FF 3 fifo_inst/Equal.wcount_r_10_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_8_s0/I0
3.395 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_8_s0/F
3.632 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.148 0.517 tINS FF 3 fifo_inst/Equal.wcount_r_2_s0/F
4.385 0.237 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
5.865 0.035 tINS FF 1 fifo_inst/rcnt_sub_5_s/COUT
5.865 0.000 tNET FF 2 fifo_inst/rcnt_sub_6_s/CIN
5.900 0.035 tINS FF 1 fifo_inst/rcnt_sub_6_s/COUT
5.900 0.000 tNET FF 2 fifo_inst/rcnt_sub_7_s/CIN
5.935 0.035 tINS FF 1 fifo_inst/rcnt_sub_7_s/COUT
5.935 0.000 tNET FF 2 fifo_inst/rcnt_sub_8_s/CIN
6.405 0.470 tINS FF 1 fifo_inst/rcnt_sub_8_s/SUM
6.642 0.237 tNET FF 1 fifo_inst/Rnum_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 49 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_8_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Rnum_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.888, 67.281%; route: 1.659, 28.705%; tC2Q: 0.232, 4.014%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%