Timing Messages

Report Title Timing Analysis Report
Design File H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\impl\gwsynthesis\ov2640x2_udp_rgmii.vg
Physical Constraints File H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\ov2640x2_udp_rgmii.cst
Timing Constraint File ---
Version V1.9.9 Beta-6
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Mon Feb 26 17:58:19 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.85V -40C ES
Hold Delay Model Fast 0.95V 100C ES
Numbers of Paths Analyzed 3723
Numbers of Endpoints Analyzed 3004
Numbers of Falling Endpoints 18
Numbers of Setup Violated Endpoints 75
Numbers of Hold Violated Endpoints 18

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
camera1_pclk Base 10.000 100.000 0.000 5.000 camera1_pclk_ibuf/I
camera2_pclk Base 10.000 100.000 0.000 5.000 camera2_pclk_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Generated 8.000 125.000 0.000 4.000 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk Generated 20.000 50.000 0.000 10.000 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT1
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk Generated 41.600 24.038 0.000 20.800 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT2

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 camera1_pclk 100.000(MHz) 140.709(MHz) 6 TOP
2 camera2_pclk 100.000(MHz) 132.896(MHz) 6 TOP
3 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk 125.000(MHz) 105.446(MHz) 9 TOP
4 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk 50.000(MHz) 173.001(MHz) 5 TOP

No timing paths to get frequency of clk!

No timing paths to get frequency of Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
camera1_pclk Setup 0.000 0
camera1_pclk Hold 0.000 0
camera2_pclk Setup 0.000 0
camera2_pclk Hold 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Setup -7.717 8
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Hold 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk Setup 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk Hold 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk Setup 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -2.204 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_7_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.253 1.852
2 -1.940 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_2_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.272 1.569
3 -1.889 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_13_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.244 1.546
4 -1.582 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_4_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.282 1.201
5 -1.529 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_3_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.282 1.149
6 -1.484 controller_top/controller/state.SIDEA_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.024 9.373
7 -1.366 controller_top/controller/state.SIDEA_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.024 9.255
8 -1.271 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_11_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.272 0.900
9 -1.271 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_6_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.272 0.900
10 -1.195 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_1_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.291 0.805
11 -1.183 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_9_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.282 0.803
12 -1.174 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_5_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.272 0.803
13 -1.174 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_12_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.272 0.803
14 -1.172 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_10_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.291 0.782
15 -1.172 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_0_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.291 0.782
16 -1.155 controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_8_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0/D camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.254 0.803
17 -1.142 UDP_Send/fifo_rdreq_s2/Q UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.003 9.051
18 -1.097 controller_top/controller/state.SIDEA_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.033 8.976
19 -1.015 UDP_Send/fifo_rdreq_s2/Q UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 -0.015 8.944
20 -0.982 controller_top/controller/cnt_2_s2/Q UDP_Send/eth_dcfifo/fifo_inst/Full_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.011 8.908
21 -0.502 controller_top/controller/state.SIDEA_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.033 8.381
22 -0.358 controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_5_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/D camera1_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 0.750 1.509
23 -0.167 controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_13_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/D camera1_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 0.761 1.308
24 -0.129 controller_top/controller/state.SIDEB_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEB Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 8.000 0.015 8.028
25 -0.018 controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_11_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/D camera1_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 0.757 1.162

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.875 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_5_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.288 0.450
2 -0.875 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_6_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.288 0.450
3 -0.866 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_7_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.280 0.450
4 -0.865 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.279 0.450
5 -0.856 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_4_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.270 0.450
6 -0.793 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_12_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.258 0.501
7 -0.753 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.279 0.538
8 -0.687 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_9_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.258 0.582
9 -0.677 controller_top/cache2/dc_fifo/fifo_inst/rbin_num_13_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.275 0.609
10 -0.462 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_11_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.265 0.815
11 -0.450 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_8_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.256 0.818
12 -0.348 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_10_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.246 0.909
13 -0.341 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.246 0.916
14 -0.325 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0/Q controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera2_pclk:[R] 0.000 -1.249 0.935
15 -0.010 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_1_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.450
16 -0.010 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_3_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.450
17 -0.010 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_4_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.450
18 -0.010 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_6_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.450
19 0.042 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_2_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.501
20 0.042 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_5_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.501
21 0.042 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_7_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.501
22 0.044 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_0_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.421 0.501
23 0.047 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_11_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.418 0.501
24 0.145 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_9_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.423 0.580
25 0.150 controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_12_s0/Q controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/D Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] camera1_pclk:[R] 0.000 -0.418 0.580

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -2.670 Camera_ETH_Formator2/fifo_aclr_s0/Q UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.294 2.049
2 -2.670 Camera_ETH_Formator2/fifo_aclr_s0/Q UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.294 2.049
3 -2.486 Camera_ETH_Formator2/fifo_aclr_s0/Q UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.294 1.865
4 -2.486 Camera_ETH_Formator2/fifo_aclr_s0/Q UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.294 1.865
5 -2.379 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_4_s6/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.249 1.747
6 -2.376 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_10_s2/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.246 1.747
7 -2.306 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_1_s6/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.251 1.672
8 -2.306 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_6_s6/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.251 1.672
9 -2.306 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_8_s6/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.251 1.672
10 -2.306 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_0_s0/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.251 1.672
11 -2.130 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_5_s2/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.255 1.492
12 -2.130 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_9_s2/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.255 1.492
13 -1.943 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/state.IDLE_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.260 1.300
14 -1.943 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/state.SIDEB_s0/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.260 1.300
15 -1.943 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/state.SIDEA_s0/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.260 1.300
16 -1.940 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_3_s6/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.258 1.300
17 -1.940 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_7_s2/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.258 1.300
18 -1.901 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/controller/cnt_2_s2/CLEAR camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 2.000 2.270 1.249
19 -1.418 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.274 0.816
20 -1.418 Camera_ETH_Formator2/fifo_aclr_s0/Q controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0/PRESET camera2_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 2.274 0.816
21 -0.808 Camera_ETH_Formator1/fifo_aclr_s0/Q controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0/PRESET camera1_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 0.766 1.714
22 -0.808 Camera_ETH_Formator1/fifo_aclr_s0/Q controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0/PRESET camera1_pclk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F] 2.000 0.766 1.714
23 -0.637 camera_init1/Init_Done_s1/Q UDP_Send/state.SEND_HEADER_s5/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 4.000 0.038 4.216
24 -0.637 camera_init1/Init_Done_s1/Q UDP_Send/cnt_header_0_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 4.000 0.038 4.216
25 -0.637 camera_init1/Init_Done_s1/Q UDP_Send/cnt_header_1_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] 4.000 0.038 4.216

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.103 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/en_div_cnt_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 0.907
2 1.103 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_8_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 0.907
3 1.103 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_9_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 0.907
4 1.103 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_12_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 0.907
5 1.109 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/Trans_Done_s2/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 0.924
6 1.109 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/mdio_oe_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 0.924
7 1.136 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_7_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.011 0.936
8 1.136 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_10_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.011 0.936
9 1.214 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_0_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.024
10 1.214 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_2_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.024
11 1.214 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_3_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.024
12 1.214 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_11_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.024
13 1.239 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/mdio_o_s2/PRESET Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 1.044
14 1.256 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/cnt_1_s2/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.066
15 1.256 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/cnt_4_s2/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.066
16 1.256 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/cnt_5_s2/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.066
17 1.256 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/state.IDLE_s0/PRESET Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.001 1.066
18 1.261 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_1_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 1.066
19 1.261 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_4_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 1.066
20 1.261 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_5_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 1.066
21 1.261 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/div_cnt_6_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 0.006 1.066
22 1.496 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/state.TA_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 1.311
23 1.496 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/state.REGAD_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 1.311
24 1.496 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/state.PHYAD_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 1.311
25 1.496 phy_reg_config/cnt_8_s0/Q phy_reg_config/mdio_bit_shift/state.OP_s0/CLEAR Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R] 0.000 -0.004 1.311

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.499 3.499 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
2 2.499 3.499 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s
3 2.499 3.499 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
4 2.501 3.501 1.000 High Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
5 2.501 3.501 1.000 High Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s
6 2.501 3.501 1.000 High Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
7 2.503 3.503 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
8 2.503 3.503 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s
9 2.503 3.503 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s
10 2.503 3.503 1.000 Low Pulse Width Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -2.204
Data Arrival Time 35.678
Data Required Time 33.474
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_7_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.826 3.143 tNET RR 1 R29C47[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_7_s0/CLK
34.208 0.382 tC2Q RR 1 R29C47[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_7_s0/Q
35.678 1.470 tNET RR 1 R25C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.573 0.891 tNET RR 1 R25C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0/CLK
33.538 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0
33.474 -0.064 tSu 1 R25C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_7_s0

Path Statistics:

Clock Skew -2.253
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.840%; route: 3.143, 82.160%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.470, 79.352%; tC2Q: 0.382, 20.648%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.891, 100.000%

Path2

Path Summary:

Slack -1.940
Data Arrival Time 35.423
Data Required Time 33.483
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_2_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.854 3.172 tNET RR 1 R25C47[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_2_s0/CLK
34.237 0.382 tC2Q RR 1 R25C47[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_2_s0/Q
35.423 1.186 tNET RR 1 R25C43[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.582 0.900 tNET RR 1 R25C43[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0/CLK
33.547 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0
33.483 -0.064 tSu 1 R25C43[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_2_s0

Path Statistics:

Clock Skew -2.272
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.707%; route: 3.172, 82.293%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.186, 75.618%; tC2Q: 0.382, 24.382%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.900, 100.000%

Path3

Path Summary:

Slack -1.889
Data Arrival Time 35.358
Data Required Time 33.469
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_13_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.812 3.129 tNET RR 1 R27C42[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_13_s0/CLK
34.194 0.382 tC2Q RR 3 R27C42[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_13_s0/Q
35.358 1.164 tNET RR 1 R27C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.568 0.886 tNET RR 1 R27C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/CLK
33.533 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0
33.469 -0.064 tSu 1 R27C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0

Path Statistics:

Clock Skew -2.244
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.905%; route: 3.129, 82.095%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.164, 75.263%; tC2Q: 0.382, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path4

Path Summary:

Slack -1.582
Data Arrival Time 35.056
Data Required Time 33.474
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_4_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.854 3.172 tNET RR 1 R25C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_4_s0/CLK
34.237 0.382 tC2Q RR 1 R25C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_4_s0/Q
35.056 0.819 tNET RR 1 R25C46[3][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.573 0.891 tNET RR 1 R25C46[3][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0/CLK
33.538 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0
33.474 -0.064 tSu 1 R25C46[3][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_4_s0

Path Statistics:

Clock Skew -2.282
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.707%; route: 3.172, 82.293%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.819, 68.158%; tC2Q: 0.382, 31.842%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.891, 100.000%

Path5

Path Summary:

Slack -1.529
Data Arrival Time 35.003
Data Required Time 33.474
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_3_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.854 3.172 tNET RR 1 R25C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_3_s0/CLK
34.237 0.382 tC2Q RR 1 R25C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_3_s0/Q
35.003 0.766 tNET RR 1 R25C46[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.573 0.891 tNET RR 1 R25C46[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0/CLK
33.538 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0
33.474 -0.064 tSu 1 R25C46[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_3_s0

Path Statistics:

Clock Skew -2.282
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.707%; route: 3.172, 82.293%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.766, 66.703%; tC2Q: 0.382, 33.297%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.891, 100.000%

Path6

Path Summary:

Slack -1.484
Data Arrival Time 10.948
Data Required Time 9.464
From controller_top/controller/state.SIDEA_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.575 0.893 tNET RR 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLK
1.958 0.382 tC2Q RR 17 R24C48[1][B] controller_top/controller/state.SIDEA_s0/Q
2.949 0.991 tNET RR 1 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/I1
3.364 0.415 tINS RR 7 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/F
3.714 0.350 tNET RR 1 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/I1
3.976 0.262 tINS RR 9 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/F
4.348 0.371 tNET RR 1 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/I1
4.809 0.461 tINS RR 5 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/F
5.515 0.706 tNET RR 1 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/I1
6.013 0.498 tINS RR 2 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/F
6.173 0.160 tNET RR 1 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/I1
6.699 0.526 tINS RR 2 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/F
7.429 0.730 tNET RR 2 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/I0
7.985 0.556 tINS RF 1 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/COUT
7.985 0.000 tNET FF 2 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/CIN
8.035 0.050 tINS FR 1 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/COUT
8.035 0.000 tNET RR 2 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/CIN
8.085 0.050 tINS RR 1 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/COUT
8.085 0.000 tNET RR 2 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/CIN
8.135 0.050 tINS RR 1 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/COUT
8.135 0.000 tNET RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/CIN
8.185 0.050 tINS RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/COUT
8.779 0.594 tNET RR 1 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/I2
9.194 0.415 tINS RR 4 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/F
10.948 1.754 tNET RR 1 BSRAM_R10[14] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.551 0.869 tNET RR 1 BSRAM_R10[14] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB
9.464 -0.087 tSu 1 BSRAM_R10[14] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s

Path Statistics:

Clock Skew -0.024
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay cell: 3.334, 35.569%; route: 5.656, 60.349%; tC2Q: 0.382, 4.081%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path7

Path Summary:

Slack -1.366
Data Arrival Time 10.830
Data Required Time 9.464
From controller_top/controller/state.SIDEA_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.575 0.893 tNET RR 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLK
1.958 0.382 tC2Q RR 17 R24C48[1][B] controller_top/controller/state.SIDEA_s0/Q
2.949 0.991 tNET RR 1 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/I1
3.364 0.415 tINS RR 7 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/F
3.714 0.350 tNET RR 1 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/I1
3.976 0.262 tINS RR 9 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/F
4.348 0.371 tNET RR 1 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/I1
4.809 0.461 tINS RR 5 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/F
5.515 0.706 tNET RR 1 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/I1
6.013 0.498 tINS RR 2 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/F
6.173 0.160 tNET RR 1 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/I1
6.699 0.526 tINS RR 2 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/F
7.429 0.730 tNET RR 2 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/I0
7.985 0.556 tINS RF 1 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/COUT
7.985 0.000 tNET FF 2 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/CIN
8.035 0.050 tINS FR 1 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/COUT
8.035 0.000 tNET RR 2 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/CIN
8.085 0.050 tINS RR 1 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/COUT
8.085 0.000 tNET RR 2 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/CIN
8.135 0.050 tINS RR 1 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/COUT
8.135 0.000 tNET RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/CIN
8.185 0.050 tINS RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/COUT
8.779 0.594 tNET RR 1 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/I2
9.194 0.415 tINS RR 4 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/F
10.830 1.636 tNET RR 1 BSRAM_R10[12] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.551 0.869 tNET RR 1 BSRAM_R10[12] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB
9.464 -0.087 tSu 1 BSRAM_R10[12] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew -0.024
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay cell: 3.334, 36.021%; route: 5.539, 59.846%; tC2Q: 0.382, 4.133%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path8

Path Summary:

Slack -1.271
Data Arrival Time 34.740
Data Required Time 33.469
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_11_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.840 3.158 tNET RR 1 R27C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_11_s0/CLK
34.222 0.382 tC2Q RR 1 R27C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_11_s0/Q
34.740 0.517 tNET RR 1 R27C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.568 0.886 tNET RR 1 R27C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/CLK
33.533 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0
33.469 -0.064 tSu 1 R27C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0

Path Statistics:

Clock Skew -2.272
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.773%; route: 3.158, 82.227%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.517, 57.500%; tC2Q: 0.382, 42.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path9

Path Summary:

Slack -1.271
Data Arrival Time 34.726
Data Required Time 33.455
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_6_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.826 3.143 tNET RR 1 R29C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_6_s0/CLK
34.208 0.382 tC2Q RR 1 R29C47[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_6_s0/Q
34.726 0.517 tNET RR 1 R29C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.553 0.871 tNET RR 1 R29C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0/CLK
33.518 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0
33.455 -0.064 tSu 1 R29C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_6_s0

Path Statistics:

Clock Skew -2.272
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.840%; route: 3.143, 82.160%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.517, 57.500%; tC2Q: 0.382, 42.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.871, 100.000%

Path10

Path Summary:

Slack -1.195
Data Arrival Time 34.654
Data Required Time 33.460
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_1_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.849 3.167 tNET RR 1 R27C46[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_1_s0/CLK
34.232 0.382 tC2Q RR 1 R27C46[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_1_s0/Q
34.654 0.422 tNET RR 1 R27C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.558 0.876 tNET RR 1 R27C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0/CLK
33.523 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0
33.460 -0.064 tSu 1 R27C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_1_s0

Path Statistics:

Clock Skew -2.291
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.730%; route: 3.167, 82.270%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.422, 52.484%; tC2Q: 0.382, 47.516%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path11

Path Summary:

Slack -1.183
Data Arrival Time 34.619
Data Required Time 33.436
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_9_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.816 3.134 tNET RR 1 R29C44[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_9_s0/CLK
34.199 0.382 tC2Q RR 1 R29C44[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_9_s0/Q
34.619 0.420 tNET RR 1 R29C45[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.535 0.852 tNET RR 1 R29C45[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0/CLK
33.500 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0
33.436 -0.064 tSu 1 R29C45[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_9_s0

Path Statistics:

Clock Skew -2.282
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.884%; route: 3.134, 82.116%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.420, 52.336%; tC2Q: 0.382, 47.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path12

Path Summary:

Slack -1.174
Data Arrival Time 34.638
Data Required Time 33.465
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_5_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C41[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_5_s0/CLK
34.218 0.382 tC2Q RR 1 R25C41[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_5_s0/Q
34.638 0.420 tNET RR 1 R25C41[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.563 0.881 tNET RR 1 R25C41[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/CLK
33.528 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0
33.465 -0.064 tSu 1 R25C41[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0

Path Statistics:

Clock Skew -2.272
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.420, 52.336%; tC2Q: 0.382, 47.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.881, 100.000%

Path13

Path Summary:

Slack -1.174
Data Arrival Time 34.633
Data Required Time 33.460
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_12_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.831 3.148 tNET RR 1 R27C48[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_12_s0/CLK
34.213 0.382 tC2Q RR 1 R27C48[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_12_s0/Q
34.633 0.420 tNET RR 1 R27C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.558 0.876 tNET RR 1 R27C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0/CLK
33.523 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0
33.460 -0.064 tSu 1 R27C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_12_s0

Path Statistics:

Clock Skew -2.272
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.817%; route: 3.148, 82.183%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.420, 52.336%; tC2Q: 0.382, 47.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path14

Path Summary:

Slack -1.172
Data Arrival Time 34.632
Data Required Time 33.460
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_10_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.849 3.167 tNET RR 1 R27C46[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_10_s0/CLK
34.232 0.382 tC2Q RR 1 R27C46[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_10_s0/Q
34.632 0.400 tNET RR 1 R27C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.558 0.876 tNET RR 1 R27C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0/CLK
33.523 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0
33.460 -0.064 tSu 1 R27C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_10_s0

Path Statistics:

Clock Skew -2.291
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.730%; route: 3.167, 82.270%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 51.118%; tC2Q: 0.382, 48.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path15

Path Summary:

Slack -1.172
Data Arrival Time 34.646
Data Required Time 33.474
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_0_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.864 3.181 tNET RR 1 R25C46[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_0_s0/CLK
34.246 0.382 tC2Q RR 1 R25C46[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_0_s0/Q
34.646 0.400 tNET RR 1 R25C46[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.573 0.891 tNET RR 1 R25C46[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0/CLK
33.538 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0
33.474 -0.064 tSu 1 R25C46[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_0_s0

Path Statistics:

Clock Skew -2.291
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.664%; route: 3.181, 82.336%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 51.118%; tC2Q: 0.382, 48.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.891, 100.000%

Path16

Path Summary:

Slack -1.155
Data Arrival Time 34.600
Data Required Time 33.445
From controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_8_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.798 3.115 tNET RR 1 R29C42[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_8_s0/CLK
34.180 0.382 tC2Q RR 1 R29C42[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wptr_8_s0/Q
34.600 0.420 tNET RR 1 R29C42[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.544 0.862 tNET RR 1 R29C42[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0/CLK
33.509 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0
33.445 -0.064 tSu 1 R29C42[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rq1_wptr_8_s0

Path Statistics:

Clock Skew -2.254
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.972%; route: 3.115, 82.028%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.420, 52.336%; tC2Q: 0.382, 47.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%

Path17

Path Summary:

Slack -1.142
Data Arrival Time 10.596
Data Required Time 9.455
From UDP_Send/fifo_rdreq_s2
To UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_1_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.545 0.863 tNET RR 1 R15C42[0][A] UDP_Send/fifo_rdreq_s2/CLK
1.928 0.382 tC2Q RR 4 R15C42[0][A] UDP_Send/fifo_rdreq_s2/Q
3.383 1.455 tNET RR 1 R11C54[2][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_2_s6/I1
3.844 0.461 tINS RR 6 R11C54[2][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_2_s6/F
4.359 0.515 tNET RR 1 R12C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_5_s6/I3
4.774 0.415 tINS RR 7 R12C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_5_s6/F
4.937 0.162 tNET RR 1 R13C55[3][A] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_8_s6/I3
5.227 0.290 tINS RF 6 R13C55[3][A] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_8_s6/F
5.258 0.031 tNET FF 1 R13C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.rgraynext_9_s1/I2
5.673 0.415 tINS FR 5 R13C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.rgraynext_9_s1/F
6.355 0.683 tNET RR 1 R13C50[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_12_s2/I2
6.877 0.521 tINS RR 2 R13C50[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_12_s2/F
7.822 0.945 tNET RR 2 R15C55[0][A] UDP_Send/eth_dcfifo/fifo_inst/n123_s0/I0
8.378 0.556 tINS RF 2 R15C55[0][A] UDP_Send/eth_dcfifo/fifo_inst/n123_s0/COUT
9.183 0.805 tNET FF 1 R11C54[3][A] UDP_Send/eth_dcfifo/fifo_inst/n37_s1/I2
9.598 0.415 tINS FR 2 R11C54[3][A] UDP_Send/eth_dcfifo/fifo_inst/n37_s1/F
10.597 0.999 tNET RR 1 BSRAM_R10[17] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.542 0.860 tNET RR 1 BSRAM_R10[17] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB
9.455 -0.087 tSu 1 BSRAM_R10[17] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_1_s

Path Statistics:

Clock Skew -0.003
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.863, 100.000%
Arrival Data Path Delay cell: 3.074, 33.959%; route: 5.595, 61.815%; tC2Q: 0.382, 4.226%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path18

Path Summary:

Slack -1.097
Data Arrival Time 10.551
Data Required Time 9.455
From controller_top/controller/state.SIDEA_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.575 0.893 tNET RR 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLK
1.958 0.382 tC2Q RR 17 R24C48[1][B] controller_top/controller/state.SIDEA_s0/Q
2.949 0.991 tNET RR 1 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/I1
3.364 0.415 tINS RR 7 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/F
3.714 0.350 tNET RR 1 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/I1
3.976 0.262 tINS RR 9 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/F
4.348 0.371 tNET RR 1 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/I1
4.809 0.461 tINS RR 5 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/F
5.515 0.706 tNET RR 1 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/I1
6.013 0.498 tINS RR 2 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/F
6.173 0.160 tNET RR 1 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/I1
6.699 0.526 tINS RR 2 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/F
7.429 0.730 tNET RR 2 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/I0
7.985 0.556 tINS RF 1 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/COUT
7.985 0.000 tNET FF 2 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/CIN
8.035 0.050 tINS FR 1 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/COUT
8.035 0.000 tNET RR 2 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/CIN
8.085 0.050 tINS RR 1 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/COUT
8.085 0.000 tNET RR 2 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/CIN
8.135 0.050 tINS RR 1 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/COUT
8.135 0.000 tNET RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/CIN
8.185 0.050 tINS RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/COUT
8.779 0.594 tNET RR 1 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/I2
9.194 0.415 tINS RR 4 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/F
10.551 1.357 tNET RR 1 BSRAM_R10[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.542 0.860 tNET RR 1 BSRAM_R10[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB
9.455 -0.087 tSu 1 BSRAM_R10[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s

Path Statistics:

Clock Skew -0.033
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay cell: 3.334, 37.140%; route: 5.260, 58.599%; tC2Q: 0.382, 4.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path19

Path Summary:

Slack -1.015
Data Arrival Time 10.489
Data Required Time 9.474
From UDP_Send/fifo_rdreq_s2
To UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.545 0.863 tNET RR 1 R15C42[0][A] UDP_Send/fifo_rdreq_s2/CLK
1.928 0.382 tC2Q RR 4 R15C42[0][A] UDP_Send/fifo_rdreq_s2/Q
3.383 1.455 tNET RR 1 R11C54[2][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_2_s6/I1
3.844 0.461 tINS RR 6 R11C54[2][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_2_s6/F
4.359 0.515 tNET RR 1 R12C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_5_s6/I3
4.774 0.415 tINS RR 7 R12C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_5_s6/F
4.937 0.162 tNET RR 1 R13C55[3][A] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_8_s6/I3
5.227 0.290 tINS RF 6 R13C55[3][A] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_8_s6/F
5.258 0.031 tNET FF 1 R13C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.rgraynext_9_s1/I2
5.673 0.415 tINS FR 5 R13C55[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.rgraynext_9_s1/F
6.355 0.683 tNET RR 1 R13C50[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_12_s2/I2
6.877 0.521 tINS RR 2 R13C50[3][B] UDP_Send/eth_dcfifo/fifo_inst/rbin_num_next_12_s2/F
7.822 0.945 tNET RR 2 R15C55[0][A] UDP_Send/eth_dcfifo/fifo_inst/n123_s0/I0
8.378 0.556 tINS RF 2 R15C55[0][A] UDP_Send/eth_dcfifo/fifo_inst/n123_s0/COUT
9.183 0.805 tNET FF 1 R11C54[3][A] UDP_Send/eth_dcfifo/fifo_inst/n37_s1/I2
9.598 0.415 tINS FR 2 R11C54[3][A] UDP_Send/eth_dcfifo/fifo_inst/n37_s1/F
10.489 0.891 tNET RR 1 BSRAM_R10[15] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.561 0.878 tNET RR 1 BSRAM_R10[15] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB
9.474 -0.087 tSu 1 BSRAM_R10[15] UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew 0.015
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.863, 100.000%
Arrival Data Path Delay cell: 3.074, 34.368%; route: 5.488, 61.356%; tC2Q: 0.382, 4.277%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path20

Path Summary:

Slack -0.982
Data Arrival Time 10.473
Data Required Time 9.491
From controller_top/controller/cnt_2_s2
To UDP_Send/eth_dcfifo/fifo_inst/Full_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.566 0.884 tNET RR 1 R24C49[1][A] controller_top/controller/cnt_2_s2/CLK
1.948 0.382 tC2Q RR 4 R24C49[1][A] controller_top/controller/cnt_2_s2/Q
2.298 0.350 tNET RR 1 R23C48[3][B] controller_top/controller/n121_s10/I1
2.713 0.415 tINS RR 2 R23C48[3][B] controller_top/controller/n121_s10/F
2.873 0.160 tNET RR 1 R22C48[1][B] controller_top/controller/n121_s11/I1
3.400 0.526 tINS RR 2 R22C48[1][B] controller_top/controller/n121_s11/F
3.560 0.160 tNET RR 1 R22C47[0][B] controller_top/controller/fifo_wrreq_Z_s0/I2
3.822 0.262 tINS RR 9 R22C47[0][B] controller_top/controller/fifo_wrreq_Z_s0/F
4.715 0.892 tNET RR 1 R17C48[1][B] controller_top/controller/fifo_wrreq_Z_s/I1
5.241 0.526 tINS RR 5 R17C48[1][B] controller_top/controller/fifo_wrreq_Z_s/F
5.781 0.540 tNET RR 1 R16C51[1][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_2_s1/I1
6.297 0.516 tINS RR 15 R16C51[1][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_2_s1/F
7.677 1.380 tNET RR 1 R11C51[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_3_s0/I1
8.198 0.521 tINS RR 2 R11C51[3][B] UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_3_s0/F
8.928 0.730 tNET RR 1 R15C51[2][B] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s6/I1
9.445 0.516 tINS RR 1 R15C51[2][B] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s6/F
9.447 0.003 tNET RR 1 R15C51[3][B] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s2/I3
9.945 0.498 tINS RR 1 R15C51[3][B] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s2/F
9.947 0.003 tNET RR 1 R15C51[1][A] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s0/I1
10.473 0.526 tINS RR 1 R15C51[1][A] UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s0/F
10.473 0.000 tNET RR 1 R15C51[1][A] UDP_Send/eth_dcfifo/fifo_inst/Full_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.555 0.873 tNET RR 1 R15C51[1][A] UDP_Send/eth_dcfifo/fifo_inst/Full_s0/CLK
9.491 -0.064 tSu 1 R15C51[1][A] UDP_Send/eth_dcfifo/fifo_inst/Full_s0

Path Statistics:

Clock Skew -0.011
Setup Relationship 8.000
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%
Arrival Data Path Delay cell: 4.307, 48.358%; route: 4.218, 47.348%; tC2Q: 0.382, 4.294%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.873, 100.000%

Path21

Path Summary:

Slack -0.502
Data Arrival Time 9.956
Data Required Time 9.455
From controller_top/controller/state.SIDEA_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.575 0.893 tNET RR 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLK
1.958 0.382 tC2Q RR 17 R24C48[1][B] controller_top/controller/state.SIDEA_s0/Q
2.949 0.991 tNET RR 1 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/I1
3.364 0.415 tINS RR 7 R20C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_2_s6/F
3.714 0.350 tNET RR 1 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/I1
3.976 0.262 tINS RR 9 R22C44[0][B] controller_top/cache1/dc_fifo/fifo_inst/rbin_num_next_5_s7/F
4.348 0.371 tNET RR 1 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/I1
4.809 0.461 tINS RR 5 R21C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/F
5.515 0.706 tNET RR 1 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/I1
6.013 0.498 tINS RR 2 R18C45[3][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/F
6.173 0.160 tNET RR 1 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/I1
6.699 0.526 tINS RR 2 R17C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/F
7.429 0.730 tNET RR 2 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/I0
7.985 0.556 tINS RF 1 R23C45[1][B] controller_top/cache1/dc_fifo/fifo_inst/n124_s0/COUT
7.985 0.000 tNET FF 2 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/CIN
8.035 0.050 tINS FR 1 R23C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/n125_s0/COUT
8.035 0.000 tNET RR 2 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/CIN
8.085 0.050 tINS RR 1 R23C45[2][B] controller_top/cache1/dc_fifo/fifo_inst/n126_s0/COUT
8.085 0.000 tNET RR 2 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/CIN
8.135 0.050 tINS RR 1 R23C46[0][A] controller_top/cache1/dc_fifo/fifo_inst/n127_s0/COUT
8.135 0.000 tNET RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/CIN
8.185 0.050 tINS RR 2 R23C46[0][B] controller_top/cache1/dc_fifo/fifo_inst/n128_s0/COUT
8.779 0.594 tNET RR 1 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/I2
9.194 0.415 tINS RR 4 R20C46[3][B] controller_top/cache1/dc_fifo/fifo_inst/n38_s1/F
9.956 0.762 tNET RR 1 BSRAM_R28[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.542 0.860 tNET RR 1 BSRAM_R28[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB
9.455 -0.087 tSu 1 BSRAM_R28[13] controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s

Path Statistics:

Clock Skew -0.033
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay cell: 3.334, 39.776%; route: 4.665, 55.660%; tC2Q: 0.382, 4.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path22

Path Summary:

Slack -0.358
Data Arrival Time 33.834
Data Required Time 33.477
From controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_5_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0
Launch Clk camera1_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera1_pclk
30.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
32.326 1.643 tNET RR 1 R18C41[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_5_s0/CLK
32.708 0.382 tC2Q RR 1 R18C41[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_5_s0/Q
33.834 1.126 tNET RR 1 R24C40[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.575 0.893 tNET RR 1 R24C40[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0/CLK
33.540 -0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0
33.476 -0.064 tSu 1 R24C40[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_5_s0

Path Statistics:

Clock Skew -0.750
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 29.347%; route: 1.643, 70.653%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.126, 74.648%; tC2Q: 0.382, 25.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path23

Path Summary:

Slack -0.167
Data Arrival Time 33.644
Data Required Time 33.477
From controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_13_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0
Launch Clk camera1_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera1_pclk
30.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
32.336 1.654 tNET RR 1 R22C43[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_13_s0/CLK
32.719 0.382 tC2Q RR 3 R22C43[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_13_s0/Q
33.644 0.925 tNET RR 1 R24C46[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.575 0.893 tNET RR 1 R24C46[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0/CLK
33.540 -0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0
33.476 -0.064 tSu 1 R24C46[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_13_s0

Path Statistics:

Clock Skew -0.761
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 29.213%; route: 1.654, 70.787%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.925, 70.746%; tC2Q: 0.382, 29.254%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path24

Path Summary:

Slack -0.129
Data Arrival Time 9.603
Data Required Time 9.474
From controller_top/controller/state.SIDEB_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
1.575 0.893 tNET RR 1 R24C48[1][A] controller_top/controller/state.SIDEB_s0/CLK
1.958 0.382 tC2Q RR 10 R24C48[1][A] controller_top/controller/state.SIDEB_s0/Q
2.846 0.889 tNET RR 1 R26C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_next_2_s6/I1
3.136 0.290 tINS RF 7 R26C46[3][A] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_next_2_s6/F
4.127 0.990 tNET FF 1 R26C41[1][B] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_next_5_s7/I1
4.643 0.516 tINS FR 9 R26C41[1][B] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_next_5_s7/F
5.198 0.555 tNET RR 1 R27C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/I1
5.488 0.290 tINS RF 5 R27C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_6_s1/F
5.834 0.346 tNET FF 1 R25C44[3][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/I1
6.355 0.521 tINS FR 2 R25C44[3][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_9_s2/F
6.360 0.005 tNET RR 1 R25C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/I1
6.858 0.498 tINS RR 2 R25C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rgraynext_9_s0/F
7.018 0.160 tNET RR 2 R26C44[1][B] controller_top/cache2/dc_fifo/fifo_inst/n124_s0/I0
7.574 0.556 tINS RF 1 R26C44[1][B] controller_top/cache2/dc_fifo/fifo_inst/n124_s0/COUT
7.574 0.000 tNET FF 2 R26C44[2][A] controller_top/cache2/dc_fifo/fifo_inst/n125_s0/CIN
7.624 0.050 tINS FR 1 R26C44[2][A] controller_top/cache2/dc_fifo/fifo_inst/n125_s0/COUT
7.624 0.000 tNET RR 2 R26C44[2][B] controller_top/cache2/dc_fifo/fifo_inst/n126_s0/CIN
7.674 0.050 tINS RR 1 R26C44[2][B] controller_top/cache2/dc_fifo/fifo_inst/n126_s0/COUT
7.674 0.000 tNET RR 2 R26C45[0][A] controller_top/cache2/dc_fifo/fifo_inst/n127_s0/CIN
7.724 0.050 tINS RR 1 R26C45[0][A] controller_top/cache2/dc_fifo/fifo_inst/n127_s0/COUT
7.724 0.000 tNET RR 2 R26C45[0][B] controller_top/cache2/dc_fifo/fifo_inst/n128_s0/CIN
7.774 0.050 tINS RF 2 R26C45[0][B] controller_top/cache2/dc_fifo/fifo_inst/n128_s0/COUT
8.028 0.254 tNET FF 1 R26C45[3][A] controller_top/cache2/dc_fifo/fifo_inst/n38_s1/I2
8.293 0.265 tINS FR 4 R26C45[3][A] controller_top/cache2/dc_fifo/fifo_inst/n38_s1/F
9.603 1.310 tNET RR 1 BSRAM_R28[15] controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
9.561 0.878 tNET RR 1 BSRAM_R28[15] controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB
9.474 -0.087 tSu 1 BSRAM_R28[15] controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s

Path Statistics:

Clock Skew -0.015
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay cell: 3.136, 39.069%; route: 4.509, 56.166%; tC2Q: 0.382, 4.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path25

Path Summary:

Slack -0.018
Data Arrival Time 33.504
Data Required Time 33.486
From controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_11_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0
Launch Clk camera1_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera1_pclk
30.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
32.341 1.659 tNET RR 1 R20C43[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_11_s0/CLK
32.724 0.382 tC2Q RR 1 R20C43[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wptr_11_s0/Q
33.504 0.780 tNET RR 1 R24C43[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.585 0.902 tNET RR 1 R24C43[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0/CLK
33.550 -0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0
33.486 -0.064 tSu 1 R24C43[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rq1_wptr_11_s0

Path Statistics:

Clock Skew -0.757
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 29.151%; route: 1.659, 70.849%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.780, 67.097%; tC2Q: 0.382, 32.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.875
Data Arrival Time 41.483
Data Required Time 42.358
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_5_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.033 0.351 tNET RR 1 R30C46[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_5_s0/CLK
41.210 0.176 tC2Q RF 1 R30C46[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_5_s0/Q
41.483 0.274 tNET FF 1 R30C46[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.322 1.646 tNET RR 1 R30C46[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/CLK
42.357 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0
42.358 0.001 tHld 1 R30C46[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0

Path Statistics:

Clock Skew 1.288
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 29.094%; route: 1.646, 70.906%

Path2

Path Summary:

Slack -0.875
Data Arrival Time 41.483
Data Required Time 42.358
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_6_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.033 0.351 tNET RR 1 R30C46[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_6_s0/CLK
41.210 0.176 tC2Q RF 1 R30C46[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_6_s0/Q
41.483 0.274 tNET FF 1 R30C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.322 1.646 tNET RR 1 R30C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/CLK
42.357 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0
42.358 0.001 tHld 1 R30C46[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0

Path Statistics:

Clock Skew 1.288
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 29.094%; route: 1.646, 70.906%

Path3

Path Summary:

Slack -0.866
Data Arrival Time 41.495
Data Required Time 42.361
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_7_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.045 0.363 tNET RR 1 R29C44[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_7_s0/CLK
41.221 0.176 tC2Q RF 1 R29C44[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_7_s0/Q
41.495 0.274 tNET FF 1 R29C44[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.324 1.649 tNET RR 1 R29C44[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/CLK
42.359 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0
42.361 0.001 tHld 1 R29C44[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0

Path Statistics:

Clock Skew 1.280
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 29.063%; route: 1.649, 70.937%

Path4

Path Summary:

Slack -0.865
Data Arrival Time 41.488
Data Required Time 42.354
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.038 0.356 tNET RR 1 R30C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0/CLK
41.215 0.176 tC2Q RF 1 R30C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0/Q
41.488 0.274 tNET FF 1 R30C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.317 1.642 tNET RR 1 R30C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/CLK
42.352 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
42.354 0.001 tHld 1 R30C47[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0

Path Statistics:

Clock Skew 1.279
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 29.149%; route: 1.642, 70.851%

Path5

Path Summary:

Slack -0.856
Data Arrival Time 41.512
Data Required Time 42.368
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_4_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.062 0.380 tNET RR 1 R27C43[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_4_s0/CLK
41.238 0.176 tC2Q RF 1 R27C43[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_4_s0/Q
41.512 0.274 tNET FF 1 R27C43[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.332 1.656 tNET RR 1 R27C43[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/CLK
42.367 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0
42.368 0.001 tHld 1 R27C43[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0

Path Statistics:

Clock Skew 1.270
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 28.970%; route: 1.656, 71.030%

Path6

Path Summary:

Slack -0.793
Data Arrival Time 41.551
Data Required Time 42.344
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_12_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.050 0.368 tNET RR 1 R29C43[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_12_s0/CLK
41.226 0.176 tC2Q RF 1 R29C43[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_12_s0/Q
41.551 0.325 tNET FF 1 R30C43[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.308 1.633 tNET RR 1 R30C43[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/CLK
42.343 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0
42.344 0.001 tHld 1 R30C43[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0

Path Statistics:

Clock Skew 1.258
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.368, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 29.268%; route: 1.633, 70.732%

Path7

Path Summary:

Slack -0.753
Data Arrival Time 41.576
Data Required Time 42.329
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.038 0.356 tNET RR 1 R30C47[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0/CLK
41.218 0.180 tC2Q RR 1 R30C47[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0/Q
41.576 0.358 tNET RR 1 R30C47[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.317 1.642 tNET RR 1 R30C47[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/CLK
42.352 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
42.329 -0.024 tHld 1 R30C47[0][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0

Path Statistics:

Clock Skew 1.279
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.358, 66.512%; tC2Q: 0.180, 33.488%
Required Clock Path Delay cell: 0.675, 29.149%; route: 1.642, 70.851%

Path8

Path Summary:

Slack -0.687
Data Arrival Time 41.632
Data Required Time 42.319
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_9_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.050 0.368 tNET RR 1 R29C43[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_9_s0/CLK
41.230 0.180 tC2Q RR 1 R29C43[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_9_s0/Q
41.632 0.402 tNET RR 1 R30C43[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.308 1.633 tNET RR 1 R30C43[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/CLK
42.343 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0
42.319 -0.024 tHld 1 R30C43[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0

Path Statistics:

Clock Skew 1.258
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.368, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.402, 69.099%; tC2Q: 0.180, 30.901%
Required Clock Path Delay cell: 0.675, 29.268%; route: 1.633, 70.732%

Path9

Path Summary:

Slack -0.677
Data Arrival Time 41.661
Data Required Time 42.338
From controller_top/cache2/dc_fifo/fifo_inst/rbin_num_13_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.052 0.370 tNET RR 1 R27C45[0][B] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_13_s0/CLK
41.232 0.180 tC2Q RR 4 R27C45[0][B] controller_top/cache2/dc_fifo/fifo_inst/rbin_num_13_s0/Q
41.661 0.429 tNET RR 1 R27C42[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.327 1.651 tNET RR 1 R27C42[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0/CLK
42.362 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0
42.338 -0.024 tHld 1 R27C42[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_13_s0

Path Statistics:

Clock Skew 1.275
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.429, 70.431%; tC2Q: 0.180, 29.569%
Required Clock Path Delay cell: 0.675, 29.032%; route: 1.651, 70.968%

Path10

Path Summary:

Slack -0.462
Data Arrival Time 41.867
Data Required Time 42.329
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_11_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.052 0.370 tNET RR 1 R27C45[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_11_s0/CLK
41.232 0.180 tC2Q RR 1 R27C45[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_11_s0/Q
41.867 0.635 tNET RR 1 R30C45[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.317 1.642 tNET RR 1 R30C45[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/CLK
42.352 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0
42.329 -0.024 tHld 1 R30C45[2][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0

Path Statistics:

Clock Skew 1.265
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.635, 77.914%; tC2Q: 0.180, 22.086%
Required Clock Path Delay cell: 0.675, 29.149%; route: 1.642, 70.851%

Path11

Path Summary:

Slack -0.450
Data Arrival Time 41.875
Data Required Time 42.324
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_8_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.057 0.375 tNET RR 1 R27C44[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_8_s0/CLK
41.237 0.180 tC2Q RR 1 R27C44[0][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_8_s0/Q
41.875 0.638 tNET RR 1 R30C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.313 1.638 tNET RR 1 R30C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0/CLK
42.348 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0
42.324 -0.024 tHld 1 R30C44[3][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_8_s0

Path Statistics:

Clock Skew 1.256
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.638, 77.982%; tC2Q: 0.180, 22.018%
Required Clock Path Delay cell: 0.675, 29.204%; route: 1.638, 70.796%

Path12

Path Summary:

Slack -0.348
Data Arrival Time 41.971
Data Required Time 42.319
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_10_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.062 0.380 tNET RR 1 R27C43[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_10_s0/CLK
41.242 0.180 tC2Q RR 1 R27C43[1][A] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_10_s0/Q
41.971 0.729 tNET RR 1 R30C43[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.308 1.633 tNET RR 1 R30C43[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0/CLK
42.343 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0
42.319 -0.024 tHld 1 R30C43[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_10_s0

Path Statistics:

Clock Skew 1.246
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.729, 80.193%; tC2Q: 0.180, 19.807%
Required Clock Path Delay cell: 0.675, 29.268%; route: 1.633, 70.732%

Path13

Path Summary:

Slack -0.341
Data Arrival Time 41.978
Data Required Time 42.319
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.062 0.380 tNET RR 1 R27C43[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0/CLK
41.242 0.180 tC2Q RR 1 R27C43[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0/Q
41.978 0.736 tNET RR 1 R30C43[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.308 1.633 tNET RR 1 R30C43[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/CLK
42.343 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
42.319 -0.024 tHld 1 R30C43[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0

Path Statistics:

Clock Skew 1.246
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.736, 80.355%; tC2Q: 0.180, 19.645%
Required Clock Path Delay cell: 0.675, 29.268%; route: 1.633, 70.732%

Path14

Path Summary:

Slack -0.325
Data Arrival Time 42.003
Data Required Time 42.329
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera2_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.068 0.386 tNET RR 1 R26C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0/CLK
41.248 0.180 tC2Q RR 1 R26C47[1][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0/Q
42.003 0.755 tNET RR 1 R30C47[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera2_pclk
40.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
42.317 1.642 tNET RR 1 R30C47[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/CLK
42.352 0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
42.329 -0.024 tHld 1 R30C47[2][B] controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0

Path Statistics:

Clock Skew 1.249
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.755, 80.749%; tC2Q: 0.180, 19.251%
Required Clock Path Delay cell: 0.675, 29.149%; route: 1.642, 70.851%

Path15

Path Summary:

Slack -0.010
Data Arrival Time 41.531
Data Required Time 41.540
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_1_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.081 0.398 tNET RR 1 R20C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_1_s0/CLK
41.257 0.176 tC2Q RF 1 R20C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_1_s0/Q
41.531 0.274 tNET FF 1 R20C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.504 0.828 tNET RR 1 R20C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/CLK
41.539 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
41.540 0.001 tHld 1 R20C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 44.915%; route: 0.828, 55.085%

Path16

Path Summary:

Slack -0.010
Data Arrival Time 41.524
Data Required Time 41.534
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_3_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.074 0.392 tNET RR 1 R23C42[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_3_s0/CLK
41.250 0.176 tC2Q RF 1 R23C42[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_3_s0/Q
41.524 0.274 tNET FF 1 R23C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.497 0.822 tNET RR 1 R23C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/CLK
41.532 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
41.534 0.001 tHld 1 R23C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 45.112%; route: 0.822, 54.888%

Path17

Path Summary:

Slack -0.010
Data Arrival Time 41.528
Data Required Time 41.538
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_4_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.078 0.396 tNET RR 1 R21C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_4_s0/CLK
41.255 0.176 tC2Q RF 1 R21C42[0][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_4_s0/Q
41.528 0.274 tNET FF 1 R21C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.502 0.826 tNET RR 1 R21C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0/CLK
41.537 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0
41.538 0.001 tHld 1 R21C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_4_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 44.981%; route: 0.826, 55.019%

Path18

Path Summary:

Slack -0.010
Data Arrival Time 41.526
Data Required Time 41.536
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_6_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.076 0.394 tNET RR 1 R22C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_6_s0/CLK
41.252 0.176 tC2Q RF 1 R22C42[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_6_s0/Q
41.526 0.274 tNET FF 1 R22C42[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.500 0.824 tNET RR 1 R22C42[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0/CLK
41.535 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0
41.536 0.001 tHld 1 R22C42[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_6_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.394, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.675, 45.046%; route: 0.824, 54.954%

Path19

Path Summary:

Slack 0.042
Data Arrival Time 41.582
Data Required Time 41.540
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_2_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.081 0.398 tNET RR 1 R20C42[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_2_s0/CLK
41.257 0.176 tC2Q RF 1 R20C42[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_2_s0/Q
41.582 0.325 tNET FF 1 R20C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.504 0.828 tNET RR 1 R20C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/CLK
41.539 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
41.540 0.001 tHld 1 R20C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 44.915%; route: 0.828, 55.085%

Path20

Path Summary:

Slack 0.042
Data Arrival Time 41.580
Data Required Time 41.538
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_5_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.078 0.396 tNET RR 1 R21C42[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_5_s0/CLK
41.255 0.176 tC2Q RF 1 R21C42[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_5_s0/Q
41.580 0.325 tNET FF 1 R21C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.502 0.826 tNET RR 1 R21C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0/CLK
41.537 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0
41.538 0.001 tHld 1 R21C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_5_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 44.981%; route: 0.826, 55.019%

Path21

Path Summary:

Slack 0.042
Data Arrival Time 41.577
Data Required Time 41.536
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_7_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.076 0.394 tNET RR 1 R22C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_7_s0/CLK
41.252 0.176 tC2Q RF 1 R22C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_7_s0/Q
41.577 0.325 tNET FF 1 R22C42[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.500 0.824 tNET RR 1 R22C42[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0/CLK
41.535 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0
41.536 0.001 tHld 1 R22C42[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_7_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.394, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 45.046%; route: 0.824, 54.954%

Path22

Path Summary:

Slack 0.044
Data Arrival Time 41.575
Data Required Time 41.531
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_0_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.074 0.392 tNET RR 1 R23C42[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_0_s0/CLK
41.250 0.176 tC2Q RF 1 R23C42[2][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_0_s0/Q
41.575 0.325 tNET FF 1 R24C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.495 0.820 tNET RR 1 R24C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/CLK
41.530 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
41.531 0.001 tHld 1 R24C42[1][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0

Path Statistics:

Clock Skew 0.421
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 45.178%; route: 0.820, 54.822%

Path23

Path Summary:

Slack 0.047
Data Arrival Time 41.580
Data Required Time 41.533
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_11_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.078 0.396 tNET RR 1 R21C44[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_11_s0/CLK
41.255 0.176 tC2Q RF 1 R21C44[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_11_s0/Q
41.580 0.325 tNET FF 1 R21C43[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.497 0.821 tNET RR 1 R21C43[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0/CLK
41.532 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0
41.533 0.001 tHld 1 R21C43[0][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_11_s0

Path Statistics:

Clock Skew 0.418
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 64.838%; tC2Q: 0.176, 35.162%
Required Clock Path Delay cell: 0.675, 45.131%; route: 0.821, 54.869%

Path24

Path Summary:

Slack 0.145
Data Arrival Time 41.656
Data Required Time 41.510
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_9_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.076 0.393 tNET RR 1 R20C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_9_s0/CLK
41.256 0.180 tC2Q RR 1 R20C45[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_9_s0/Q
41.656 0.400 tNET RR 1 R20C43[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.499 0.823 tNET RR 1 R20C43[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0/CLK
41.534 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0
41.510 -0.024 tHld 1 R20C43[2][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_9_s0

Path Statistics:

Clock Skew 0.423
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.393, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 68.966%; tC2Q: 0.180, 31.034%
Required Clock Path Delay cell: 0.675, 45.065%; route: 0.823, 54.935%

Path25

Path Summary:

Slack 0.150
Data Arrival Time 41.654
Data Required Time 41.504
From controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_12_s0
To controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk camera1_pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
41.074 0.392 tNET RR 1 R23C44[3][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_12_s0/CLK
41.254 0.180 tC2Q RR 1 R23C44[3][A] controller_top/cache1/dc_fifo/fifo_inst/Equal.rptr_12_s0/Q
41.654 0.400 tNET RR 1 R23C43[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 camera1_pclk
40.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
40.675 0.675 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
41.492 0.817 tNET RR 1 R23C43[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0/CLK
41.527 0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0
41.504 -0.024 tHld 1 R23C43[1][B] controller_top/cache1/dc_fifo/fifo_inst/Equal.wq1_rptr_12_s0

Path Statistics:

Clock Skew 0.418
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.400, 68.966%; tC2Q: 0.180, 31.034%
Required Clock Path Delay cell: 0.675, 45.263%; route: 0.817, 54.737%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -2.670
Data Arrival Time 15.884
Data Required Time 13.215
From Camera_ETH_Formator2/fifo_aclr_s0
To UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
14.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
15.884 1.136 tNET FF 1 R16C52[0][B] UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.542 0.860 tNET FF 1 R16C52[0][B] UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0/CLK
13.507 -0.035 tUnc UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0
13.215 -0.292 tSu 1 R16C52[0][B] UDP_Send/eth_dcfifo/fifo_inst/reset_w_0_s0

Path Statistics:

Clock Skew -2.294
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 19.036%; route: 1.276, 62.294%; tC2Q: 0.382, 18.670%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path2

Path Summary:

Slack -2.670
Data Arrival Time 15.884
Data Required Time 13.215
From Camera_ETH_Formator2/fifo_aclr_s0
To UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
14.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
15.884 1.136 tNET FF 1 R16C52[0][A] UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.542 0.860 tNET FF 1 R16C52[0][A] UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0/CLK
13.507 -0.035 tUnc UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0
13.215 -0.292 tSu 1 R16C52[0][A] UDP_Send/eth_dcfifo/fifo_inst/reset_w_1_s0

Path Statistics:

Clock Skew -2.294
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 19.036%; route: 1.276, 62.294%; tC2Q: 0.382, 18.670%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path3

Path Summary:

Slack -2.486
Data Arrival Time 15.701
Data Required Time 13.215
From Camera_ETH_Formator2/fifo_aclr_s0
To UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
14.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
15.701 0.953 tNET FF 1 R16C50[1][B] UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.542 0.860 tNET FF 1 R16C50[1][B] UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0/CLK
13.507 -0.035 tUnc UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0
13.215 -0.292 tSu 1 R16C50[1][B] UDP_Send/eth_dcfifo/fifo_inst/reset_r_1_s0

Path Statistics:

Clock Skew -2.294
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 20.912%; route: 1.092, 58.579%; tC2Q: 0.382, 20.509%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path4

Path Summary:

Slack -2.486
Data Arrival Time 15.701
Data Required Time 13.215
From Camera_ETH_Formator2/fifo_aclr_s0
To UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
14.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
15.701 0.953 tNET FF 1 R16C50[1][A] UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.542 0.860 tNET FF 1 R16C50[1][A] UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0/CLK
13.507 -0.035 tUnc UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0
13.215 -0.292 tSu 1 R16C50[1][A] UDP_Send/eth_dcfifo/fifo_inst/reset_r_0_s0

Path Statistics:

Clock Skew -2.294
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 20.912%; route: 1.092, 58.579%; tC2Q: 0.382, 20.509%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.860, 100.000%

Path5

Path Summary:

Slack -2.379
Data Arrival Time 35.583
Data Required Time 33.205
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_4_s6
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.583 0.835 tNET FF 1 R23C47[1][B] controller_top/controller/cnt_4_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.587 0.905 tNET RR 1 R23C47[1][B] controller_top/controller/cnt_4_s6/CLK
33.552 -0.035 tUnc controller_top/controller/cnt_4_s6
33.205 -0.347 tSu 1 R23C47[1][B] controller_top/controller/cnt_4_s6

Path Statistics:

Clock Skew -2.249
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 22.318%; route: 0.975, 55.794%; tC2Q: 0.382, 21.888%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path6

Path Summary:

Slack -2.376
Data Arrival Time 35.583
Data Required Time 33.207
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_10_s2
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.583 0.835 tNET FF 1 R22C47[0][A] controller_top/controller/cnt_10_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.590 0.908 tNET RR 1 R22C47[0][A] controller_top/controller/cnt_10_s2/CLK
33.555 -0.035 tUnc controller_top/controller/cnt_10_s2
33.207 -0.347 tSu 1 R22C47[0][A] controller_top/controller/cnt_10_s2

Path Statistics:

Clock Skew -2.246
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 22.318%; route: 0.975, 55.794%; tC2Q: 0.382, 21.888%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.908, 100.000%

Path7

Path Summary:

Slack -2.306
Data Arrival Time 35.508
Data Required Time 33.202
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_1_s6
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.508 0.760 tNET FF 1 R24C47[0][A] controller_top/controller/cnt_1_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.585 0.902 tNET RR 1 R24C47[0][A] controller_top/controller/cnt_1_s6/CLK
33.550 -0.035 tUnc controller_top/controller/cnt_1_s6
33.202 -0.347 tSu 1 R24C47[0][A] controller_top/controller/cnt_1_s6

Path Statistics:

Clock Skew -2.251
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 23.318%; route: 0.900, 53.812%; tC2Q: 0.382, 22.870%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path8

Path Summary:

Slack -2.306
Data Arrival Time 35.508
Data Required Time 33.202
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_6_s6
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.508 0.760 tNET FF 1 R24C47[1][A] controller_top/controller/cnt_6_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.585 0.902 tNET RR 1 R24C47[1][A] controller_top/controller/cnt_6_s6/CLK
33.550 -0.035 tUnc controller_top/controller/cnt_6_s6
33.202 -0.347 tSu 1 R24C47[1][A] controller_top/controller/cnt_6_s6

Path Statistics:

Clock Skew -2.251
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 23.318%; route: 0.900, 53.812%; tC2Q: 0.382, 22.870%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path9

Path Summary:

Slack -2.306
Data Arrival Time 35.508
Data Required Time 33.202
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_8_s6
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.508 0.760 tNET FF 1 R24C47[1][B] controller_top/controller/cnt_8_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.585 0.902 tNET RR 1 R24C47[1][B] controller_top/controller/cnt_8_s6/CLK
33.550 -0.035 tUnc controller_top/controller/cnt_8_s6
33.202 -0.347 tSu 1 R24C47[1][B] controller_top/controller/cnt_8_s6

Path Statistics:

Clock Skew -2.251
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 23.318%; route: 0.900, 53.812%; tC2Q: 0.382, 22.870%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path10

Path Summary:

Slack -2.306
Data Arrival Time 35.508
Data Required Time 33.202
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_0_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.508 0.760 tNET FF 1 R24C47[2][A] controller_top/controller/cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.585 0.902 tNET RR 1 R24C47[2][A] controller_top/controller/cnt_0_s0/CLK
33.550 -0.035 tUnc controller_top/controller/cnt_0_s0
33.202 -0.347 tSu 1 R24C47[2][A] controller_top/controller/cnt_0_s0

Path Statistics:

Clock Skew -2.251
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 23.318%; route: 0.900, 53.812%; tC2Q: 0.382, 22.870%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path11

Path Summary:

Slack -2.130
Data Arrival Time 35.328
Data Required Time 33.198
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_5_s2
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.328 0.580 tNET FF 1 R22C48[2][B] controller_top/controller/cnt_5_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.580 0.898 tNET RR 1 R22C48[2][B] controller_top/controller/cnt_5_s2/CLK
33.545 -0.035 tUnc controller_top/controller/cnt_5_s2
33.198 -0.347 tSu 1 R22C48[2][B] controller_top/controller/cnt_5_s2

Path Statistics:

Clock Skew -2.255
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 26.131%; route: 0.720, 48.241%; tC2Q: 0.382, 25.628%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.898, 100.000%

Path12

Path Summary:

Slack -2.130
Data Arrival Time 35.328
Data Required Time 33.198
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_9_s2
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.328 0.580 tNET FF 1 R22C48[0][A] controller_top/controller/cnt_9_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.580 0.898 tNET RR 1 R22C48[0][A] controller_top/controller/cnt_9_s2/CLK
33.545 -0.035 tUnc controller_top/controller/cnt_9_s2
33.198 -0.347 tSu 1 R22C48[0][A] controller_top/controller/cnt_9_s2

Path Statistics:

Clock Skew -2.255
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 26.131%; route: 0.720, 48.241%; tC2Q: 0.382, 25.628%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.898, 100.000%

Path13

Path Summary:

Slack -1.943
Data Arrival Time 35.136
Data Required Time 33.193
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/state.IDLE_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.136 0.387 tNET FF 1 R24C48[2][A] controller_top/controller/state.IDLE_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.575 0.893 tNET RR 1 R24C48[2][A] controller_top/controller/state.IDLE_s0/CLK
33.540 -0.035 tUnc controller_top/controller/state.IDLE_s0
33.193 -0.347 tSu 1 R24C48[2][A] controller_top/controller/state.IDLE_s0

Path Statistics:

Clock Skew -2.260
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 30.000%; route: 0.527, 40.577%; tC2Q: 0.382, 29.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path14

Path Summary:

Slack -1.943
Data Arrival Time 35.136
Data Required Time 33.193
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/state.SIDEB_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.136 0.387 tNET FF 1 R24C48[1][A] controller_top/controller/state.SIDEB_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.575 0.893 tNET RR 1 R24C48[1][A] controller_top/controller/state.SIDEB_s0/CLK
33.540 -0.035 tUnc controller_top/controller/state.SIDEB_s0
33.193 -0.347 tSu 1 R24C48[1][A] controller_top/controller/state.SIDEB_s0

Path Statistics:

Clock Skew -2.260
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 30.000%; route: 0.527, 40.577%; tC2Q: 0.382, 29.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path15

Path Summary:

Slack -1.943
Data Arrival Time 35.136
Data Required Time 33.193
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/state.SIDEA_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.136 0.387 tNET FF 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.575 0.893 tNET RR 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0/CLK
33.540 -0.035 tUnc controller_top/controller/state.SIDEA_s0
33.193 -0.347 tSu 1 R24C48[1][B] controller_top/controller/state.SIDEA_s0

Path Statistics:

Clock Skew -2.260
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 30.000%; route: 0.527, 40.577%; tC2Q: 0.382, 29.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path16

Path Summary:

Slack -1.940
Data Arrival Time 35.136
Data Required Time 33.195
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_3_s6
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.136 0.387 tNET FF 1 R23C48[1][A] controller_top/controller/cnt_3_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.578 0.896 tNET RR 1 R23C48[1][A] controller_top/controller/cnt_3_s6/CLK
33.543 -0.035 tUnc controller_top/controller/cnt_3_s6
33.195 -0.347 tSu 1 R23C48[1][A] controller_top/controller/cnt_3_s6

Path Statistics:

Clock Skew -2.258
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 30.000%; route: 0.527, 40.577%; tC2Q: 0.382, 29.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path17

Path Summary:

Slack -1.940
Data Arrival Time 35.136
Data Required Time 33.195
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_7_s2
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.136 0.387 tNET FF 1 R23C48[2][B] controller_top/controller/cnt_7_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.578 0.896 tNET RR 1 R23C48[2][B] controller_top/controller/cnt_7_s2/CLK
33.543 -0.035 tUnc controller_top/controller/cnt_7_s2
33.195 -0.347 tSu 1 R23C48[2][B] controller_top/controller/cnt_7_s2

Path Statistics:

Clock Skew -2.258
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 30.000%; route: 0.527, 40.577%; tC2Q: 0.382, 29.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path18

Path Summary:

Slack -1.901
Data Arrival Time 35.084
Data Required Time 33.183
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/controller/cnt_2_s2
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.000 30.000 active clock edge time
30.000 0.000 camera2_pclk
30.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
30.683 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
33.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
34.218 0.382 tC2Q RR 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
34.358 0.140 tNET RR 1 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/I1
34.748 0.390 tINS RF 18 R25C49[1][A] controller_top/controller/fifo_aclr_Z_s/F
35.084 0.336 tNET FF 1 R24C49[1][A] controller_top/controller/cnt_2_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
32.000 32.000 active clock edge time
32.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
32.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
33.566 0.884 tNET RR 1 R24C49[1][A] controller_top/controller/cnt_2_s2/CLK
33.531 -0.035 tUnc controller_top/controller/cnt_2_s2
33.183 -0.347 tSu 1 R24C49[1][A] controller_top/controller/cnt_2_s2

Path Statistics:

Clock Skew -2.270
Setup Relationship 2.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.390, 31.231%; route: 0.476, 38.138%; tC2Q: 0.382, 30.631%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%

Path19

Path Summary:

Slack -1.418
Data Arrival Time 14.652
Data Required Time 13.234
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.203 0.368 tC2Q RF 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.652 0.449 tNET FF 1 R26C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.562 0.880 tNET FF 1 R26C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0/CLK
13.527 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0
13.234 -0.292 tSu 1 R26C48[1][B] controller_top/cache2/dc_fifo/fifo_inst/reset_r_1_s0

Path Statistics:

Clock Skew -2.274
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.449, 54.977%; tC2Q: 0.368, 45.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.880, 100.000%

Path20

Path Summary:

Slack -1.418
Data Arrival Time 14.652
Data Required Time 13.234
From Camera_ETH_Formator2/fifo_aclr_s0
To controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0
Launch Clk camera2_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 IOB79[B] camera2_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOB79[B] camera2_pclk_ibuf/O
13.836 3.153 tNET RR 1 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/CLK
14.203 0.368 tC2Q RF 5 R25C49[0][A] Camera_ETH_Formator2/fifo_aclr_s0/Q
14.652 0.449 tNET FF 1 R26C48[2][A] controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.562 0.880 tNET FF 1 R26C48[2][A] controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0/CLK
13.527 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0
13.234 -0.292 tSu 1 R26C48[2][A] controller_top/cache2/dc_fifo/fifo_inst/reset_r_0_s0

Path Statistics:

Clock Skew -2.274
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 17.794%; route: 3.153, 82.206%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.449, 54.977%; tC2Q: 0.368, 45.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.880, 100.000%

Path21

Path Summary:

Slack -0.808
Data Arrival Time 14.052
Data Required Time 13.244
From Camera_ETH_Formator1/fifo_aclr_s0
To controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0
Launch Clk camera1_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera1_pclk
10.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
12.338 1.656 tNET RR 1 R25C54[0][A] Camera_ETH_Formator1/fifo_aclr_s0/CLK
12.706 0.368 tC2Q RF 5 R25C54[0][A] Camera_ETH_Formator1/fifo_aclr_s0/Q
14.052 1.346 tNET FF 1 R24C46[2][A] controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.572 0.890 tNET FF 1 R24C46[2][A] controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0/CLK
13.537 -0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0
13.244 -0.292 tSu 1 R24C46[2][A] controller_top/cache1/dc_fifo/fifo_inst/reset_r_1_s0

Path Statistics:

Clock Skew -0.766
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 29.190%; route: 1.656, 70.810%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.346, 78.556%; tC2Q: 0.368, 21.444%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.890, 100.000%

Path22

Path Summary:

Slack -0.808
Data Arrival Time 14.052
Data Required Time 13.244
From Camera_ETH_Formator1/fifo_aclr_s0
To controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0
Launch Clk camera1_pclk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 camera1_pclk
10.000 0.000 tCL RR 1 IOR18[B] camera1_pclk_ibuf/I
10.682 0.683 tINS RR 106 IOR18[B] camera1_pclk_ibuf/O
12.338 1.656 tNET RR 1 R25C54[0][A] Camera_ETH_Formator1/fifo_aclr_s0/CLK
12.706 0.368 tC2Q RF 5 R25C54[0][A] Camera_ETH_Formator1/fifo_aclr_s0/Q
14.052 1.346 tNET FF 1 R24C46[2][B] controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.000 12.000 active clock edge time
12.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
12.682 0.682 tCL FF 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
13.572 0.890 tNET FF 1 R24C46[2][B] controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0/CLK
13.537 -0.035 tUnc controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0
13.244 -0.292 tSu 1 R24C46[2][B] controller_top/cache1/dc_fifo/fifo_inst/reset_r_0_s0

Path Statistics:

Clock Skew -0.766
Setup Relationship 2.000
Logic Level 1
Arrival Clock Path Delay cell: 0.683, 29.190%; route: 1.656, 70.810%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.346, 78.556%; tC2Q: 0.368, 21.444%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.890, 100.000%

Path23

Path Summary:

Slack -0.637
Data Arrival Time 25.802
Data Required Time 25.165
From camera_init1/Init_Done_s1
To UDP_Send/state.SEND_HEADER_s5
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
20.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
21.585 0.903 tNET RR 1 R20C57[1][A] camera_init1/Init_Done_s1/CLK
21.968 0.382 tC2Q RR 4 R20C57[1][A] camera_init1/Init_Done_s1/Q
22.945 0.978 tNET RR 1 R16C49[1][B] UDP_Send/n1182_s2/I0
23.180 0.235 tINS RF 64 R16C49[1][B] UDP_Send/n1182_s2/F
25.802 2.621 tNET FF 1 R16C48[2][A] UDP_Send/state.SEND_HEADER_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
24.000 24.000 active clock edge time
24.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
24.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
25.547 0.865 tNET RR 1 R16C48[2][A] UDP_Send/state.SEND_HEADER_s5/CLK
25.512 -0.035 tUnc UDP_Send/state.SEND_HEADER_s5
25.165 -0.347 tSu 1 R16C48[2][A] UDP_Send/state.SEND_HEADER_s5

Path Statistics:

Clock Skew -0.038
Setup Relationship 4.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay cell: 0.235, 5.574%; route: 3.599, 85.354%; tC2Q: 0.382, 9.072%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path24

Path Summary:

Slack -0.637
Data Arrival Time 25.802
Data Required Time 25.165
From camera_init1/Init_Done_s1
To UDP_Send/cnt_header_0_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
20.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
21.585 0.903 tNET RR 1 R20C57[1][A] camera_init1/Init_Done_s1/CLK
21.968 0.382 tC2Q RR 4 R20C57[1][A] camera_init1/Init_Done_s1/Q
22.945 0.978 tNET RR 1 R16C49[1][B] UDP_Send/n1182_s2/I0
23.180 0.235 tINS RF 64 R16C49[1][B] UDP_Send/n1182_s2/F
25.802 2.621 tNET FF 1 R16C48[1][A] UDP_Send/cnt_header_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
24.000 24.000 active clock edge time
24.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
24.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
25.547 0.865 tNET RR 1 R16C48[1][A] UDP_Send/cnt_header_0_s0/CLK
25.512 -0.035 tUnc UDP_Send/cnt_header_0_s0
25.165 -0.347 tSu 1 R16C48[1][A] UDP_Send/cnt_header_0_s0

Path Statistics:

Clock Skew -0.038
Setup Relationship 4.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay cell: 0.235, 5.574%; route: 3.599, 85.354%; tC2Q: 0.382, 9.072%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path25

Path Summary:

Slack -0.637
Data Arrival Time 25.802
Data Required Time 25.165
From camera_init1/Init_Done_s1
To UDP_Send/cnt_header_1_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
20.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
21.585 0.903 tNET RR 1 R20C57[1][A] camera_init1/Init_Done_s1/CLK
21.968 0.382 tC2Q RR 4 R20C57[1][A] camera_init1/Init_Done_s1/Q
22.945 0.978 tNET RR 1 R16C49[1][B] UDP_Send/n1182_s2/I0
23.180 0.235 tINS RF 64 R16C49[1][B] UDP_Send/n1182_s2/F
25.802 2.621 tNET FF 1 R16C48[1][B] UDP_Send/cnt_header_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
24.000 24.000 active clock edge time
24.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
24.682 0.682 tCL RR 395 PLL_B Gowin_PLL/PLLA_inst/CLKOUT0
25.547 0.865 tNET RR 1 R16C48[1][B] UDP_Send/cnt_header_1_s0/CLK
25.512 -0.035 tUnc UDP_Send/cnt_header_1_s0
25.165 -0.347 tSu 1 R16C48[1][B] UDP_Send/cnt_header_1_s0

Path Statistics:

Clock Skew -0.038
Setup Relationship 4.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay cell: 0.235, 5.574%; route: 3.599, 85.354%; tC2Q: 0.382, 9.072%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.103
Data Arrival Time 1.952
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/en_div_cnt_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.952 0.232 tNET RR 1 R13C57[2][B] phy_reg_config/mdio_bit_shift/en_div_cnt_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R13C57[2][B] phy_reg_config/mdio_bit_shift/en_div_cnt_s0/CLK
0.850 -0.189 tHld 1 R13C57[2][B] phy_reg_config/mdio_bit_shift/en_div_cnt_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 40.220%; route: 0.362, 39.945%; tC2Q: 0.180, 19.835%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path2

Path Summary:

Slack 1.103
Data Arrival Time 1.952
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_8_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.952 0.232 tNET RR 1 R13C57[1][A] phy_reg_config/mdio_bit_shift/div_cnt_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R13C57[1][A] phy_reg_config/mdio_bit_shift/div_cnt_8_s0/CLK
0.850 -0.189 tHld 1 R13C57[1][A] phy_reg_config/mdio_bit_shift/div_cnt_8_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 40.220%; route: 0.362, 39.945%; tC2Q: 0.180, 19.835%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path3

Path Summary:

Slack 1.103
Data Arrival Time 1.952
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_9_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.952 0.232 tNET RR 1 R13C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R13C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_9_s0/CLK
0.850 -0.189 tHld 1 R13C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_9_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 40.220%; route: 0.362, 39.945%; tC2Q: 0.180, 19.835%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path4

Path Summary:

Slack 1.103
Data Arrival Time 1.952
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_12_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.952 0.232 tNET RR 1 R13C57[0][B] phy_reg_config/mdio_bit_shift/div_cnt_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R13C57[0][B] phy_reg_config/mdio_bit_shift/div_cnt_12_s0/CLK
0.850 -0.189 tHld 1 R13C57[0][B] phy_reg_config/mdio_bit_shift/div_cnt_12_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 40.220%; route: 0.362, 39.945%; tC2Q: 0.180, 19.835%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path5

Path Summary:

Slack 1.109
Data Arrival Time 1.968
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/Trans_Done_s2
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.968 0.249 tNET RR 1 R14C58[0][A] phy_reg_config/mdio_bit_shift/Trans_Done_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R14C58[0][A] phy_reg_config/mdio_bit_shift/Trans_Done_s2/CLK
0.860 -0.189 tHld 1 R14C58[0][A] phy_reg_config/mdio_bit_shift/Trans_Done_s2

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 39.513%; route: 0.379, 41.001%; tC2Q: 0.180, 19.486%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path6

Path Summary:

Slack 1.109
Data Arrival Time 1.968
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/mdio_oe_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.968 0.249 tNET RR 1 R14C58[1][B] phy_reg_config/mdio_bit_shift/mdio_oe_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R14C58[1][B] phy_reg_config/mdio_bit_shift/mdio_oe_s0/CLK
0.860 -0.189 tHld 1 R14C58[1][B] phy_reg_config/mdio_bit_shift/mdio_oe_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 39.513%; route: 0.379, 41.001%; tC2Q: 0.180, 19.486%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path7

Path Summary:

Slack 1.136
Data Arrival Time 1.981
Data Required Time 0.845
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_7_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.981 0.261 tNET RR 1 R13C56[0][A] phy_reg_config/mdio_bit_shift/div_cnt_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.033 0.351 tNET RR 1 R13C56[0][A] phy_reg_config/mdio_bit_shift/div_cnt_7_s0/CLK
0.845 -0.189 tHld 1 R13C56[0][A] phy_reg_config/mdio_bit_shift/div_cnt_7_s0

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 38.985%; route: 0.391, 41.789%; tC2Q: 0.180, 19.226%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%

Path8

Path Summary:

Slack 1.136
Data Arrival Time 1.981
Data Required Time 0.845
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_10_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
1.981 0.261 tNET RR 1 R13C56[3][A] phy_reg_config/mdio_bit_shift/div_cnt_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.033 0.351 tNET RR 1 R13C56[3][A] phy_reg_config/mdio_bit_shift/div_cnt_10_s0/CLK
0.845 -0.189 tHld 1 R13C56[3][A] phy_reg_config/mdio_bit_shift/div_cnt_10_s0

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 38.985%; route: 0.391, 41.789%; tC2Q: 0.180, 19.226%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%

Path9

Path Summary:

Slack 1.214
Data Arrival Time 2.068
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_0_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.068 0.349 tNET RR 1 R14C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R14C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_0_s0/CLK
0.855 -0.189 tHld 1 R14C57[1][B] phy_reg_config/mdio_bit_shift/div_cnt_0_s0

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 35.653%; route: 0.479, 46.764%; tC2Q: 0.180, 17.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path10

Path Summary:

Slack 1.214
Data Arrival Time 2.068
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_2_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.068 0.349 tNET RR 1 R14C57[2][B] phy_reg_config/mdio_bit_shift/div_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R14C57[2][B] phy_reg_config/mdio_bit_shift/div_cnt_2_s0/CLK
0.855 -0.189 tHld 1 R14C57[2][B] phy_reg_config/mdio_bit_shift/div_cnt_2_s0

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 35.653%; route: 0.479, 46.764%; tC2Q: 0.180, 17.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path11

Path Summary:

Slack 1.214
Data Arrival Time 2.068
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_3_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.068 0.349 tNET RR 1 R14C57[2][A] phy_reg_config/mdio_bit_shift/div_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R14C57[2][A] phy_reg_config/mdio_bit_shift/div_cnt_3_s0/CLK
0.855 -0.189 tHld 1 R14C57[2][A] phy_reg_config/mdio_bit_shift/div_cnt_3_s0

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 35.653%; route: 0.479, 46.764%; tC2Q: 0.180, 17.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path12

Path Summary:

Slack 1.214
Data Arrival Time 2.068
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_11_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.068 0.349 tNET RR 1 R14C57[3][A] phy_reg_config/mdio_bit_shift/div_cnt_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R14C57[3][A] phy_reg_config/mdio_bit_shift/div_cnt_11_s0/CLK
0.855 -0.189 tHld 1 R14C57[3][A] phy_reg_config/mdio_bit_shift/div_cnt_11_s0

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 35.653%; route: 0.479, 46.764%; tC2Q: 0.180, 17.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path13

Path Summary:

Slack 1.239
Data Arrival Time 2.088
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/mdio_o_s2
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.088 0.369 tNET RR 1 R13C59[0][A] phy_reg_config/mdio_bit_shift/mdio_o_s2/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R13C59[0][A] phy_reg_config/mdio_bit_shift/mdio_o_s2/CLK
0.850 -0.189 tHld 1 R13C59[0][A] phy_reg_config/mdio_bit_shift/mdio_o_s2

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.970%; route: 0.499, 47.784%; tC2Q: 0.180, 17.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path14

Path Summary:

Slack 1.256
Data Arrival Time 2.111
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/cnt_1_s2
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R15C56[3][A] phy_reg_config/mdio_bit_shift/cnt_1_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R15C56[3][A] phy_reg_config/mdio_bit_shift/cnt_1_s2/CLK
0.855 -0.189 tHld 1 R15C56[3][A] phy_reg_config/mdio_bit_shift/cnt_1_s2

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path15

Path Summary:

Slack 1.256
Data Arrival Time 2.111
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/cnt_4_s2
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R15C56[0][B] phy_reg_config/mdio_bit_shift/cnt_4_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R15C56[0][B] phy_reg_config/mdio_bit_shift/cnt_4_s2/CLK
0.855 -0.189 tHld 1 R15C56[0][B] phy_reg_config/mdio_bit_shift/cnt_4_s2

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path16

Path Summary:

Slack 1.256
Data Arrival Time 2.111
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/cnt_5_s2
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R15C56[0][A] phy_reg_config/mdio_bit_shift/cnt_5_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R15C56[0][A] phy_reg_config/mdio_bit_shift/cnt_5_s2/CLK
0.855 -0.189 tHld 1 R15C56[0][A] phy_reg_config/mdio_bit_shift/cnt_5_s2

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path17

Path Summary:

Slack 1.256
Data Arrival Time 2.111
Data Required Time 0.855
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/state.IDLE_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R15C56[1][A] phy_reg_config/mdio_bit_shift/state.IDLE_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.043 0.361 tNET RR 1 R15C56[1][A] phy_reg_config/mdio_bit_shift/state.IDLE_s0/CLK
0.855 -0.189 tHld 1 R15C56[1][A] phy_reg_config/mdio_bit_shift/state.IDLE_s0

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%

Path18

Path Summary:

Slack 1.261
Data Arrival Time 2.111
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_1_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R14C56[0][B] phy_reg_config/mdio_bit_shift/div_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R14C56[0][B] phy_reg_config/mdio_bit_shift/div_cnt_1_s0/CLK
0.850 -0.189 tHld 1 R14C56[0][B] phy_reg_config/mdio_bit_shift/div_cnt_1_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path19

Path Summary:

Slack 1.261
Data Arrival Time 2.111
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_4_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R14C56[2][A] phy_reg_config/mdio_bit_shift/div_cnt_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R14C56[2][A] phy_reg_config/mdio_bit_shift/div_cnt_4_s0/CLK
0.850 -0.189 tHld 1 R14C56[2][A] phy_reg_config/mdio_bit_shift/div_cnt_4_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path20

Path Summary:

Slack 1.261
Data Arrival Time 2.111
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_5_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R14C56[1][B] phy_reg_config/mdio_bit_shift/div_cnt_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R14C56[1][B] phy_reg_config/mdio_bit_shift/div_cnt_5_s0/CLK
0.850 -0.189 tHld 1 R14C56[1][B] phy_reg_config/mdio_bit_shift/div_cnt_5_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path21

Path Summary:

Slack 1.261
Data Arrival Time 2.111
Data Required Time 0.850
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/div_cnt_6_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.111 0.391 tNET RR 1 R14C56[1][A] phy_reg_config/mdio_bit_shift/div_cnt_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.038 0.356 tNET RR 1 R14C56[1][A] phy_reg_config/mdio_bit_shift/div_cnt_6_s0/CLK
0.850 -0.189 tHld 1 R14C56[1][A] phy_reg_config/mdio_bit_shift/div_cnt_6_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 34.232%; route: 0.521, 48.886%; tC2Q: 0.180, 16.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path22

Path Summary:

Slack 1.496
Data Arrival Time 2.356
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/state.TA_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.356 0.636 tNET RR 1 R15C57[2][A] phy_reg_config/mdio_bit_shift/state.TA_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R15C57[2][A] phy_reg_config/mdio_bit_shift/state.TA_s0/CLK
0.860 -0.189 tHld 1 R15C57[2][A] phy_reg_config/mdio_bit_shift/state.TA_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 27.836%; route: 0.766, 58.437%; tC2Q: 0.180, 13.727%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path23

Path Summary:

Slack 1.496
Data Arrival Time 2.356
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/state.REGAD_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.356 0.636 tNET RR 1 R15C57[2][B] phy_reg_config/mdio_bit_shift/state.REGAD_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R15C57[2][B] phy_reg_config/mdio_bit_shift/state.REGAD_s0/CLK
0.860 -0.189 tHld 1 R15C57[2][B] phy_reg_config/mdio_bit_shift/state.REGAD_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 27.836%; route: 0.766, 58.437%; tC2Q: 0.180, 13.727%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path24

Path Summary:

Slack 1.496
Data Arrival Time 2.356
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/state.PHYAD_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.356 0.636 tNET RR 1 R15C57[3][A] phy_reg_config/mdio_bit_shift/state.PHYAD_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R15C57[3][A] phy_reg_config/mdio_bit_shift/state.PHYAD_s0/CLK
0.860 -0.189 tHld 1 R15C57[3][A] phy_reg_config/mdio_bit_shift/state.PHYAD_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 27.836%; route: 0.766, 58.437%; tC2Q: 0.180, 13.727%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path25

Path Summary:

Slack 1.496
Data Arrival Time 2.356
Data Required Time 0.860
From phy_reg_config/cnt_8_s0
To phy_reg_config/mdio_bit_shift/state.OP_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.045 0.363 tNET RR 1 R11C57[0][B] phy_reg_config/cnt_8_s0/CLK
1.225 0.180 tC2Q RR 3 R11C57[0][B] phy_reg_config/cnt_8_s0/Q
1.347 0.123 tNET RR 1 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/I1
1.530 0.183 tINS RR 2 R12C57[0][A] phy_reg_config/mdio_bit_shift/n100_s2/F
1.537 0.008 tNET RR 1 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/I0
1.720 0.183 tINS RR 34 R12C57[1][A] phy_reg_config/mdio_bit_shift/n100_s1/F
2.356 0.636 tNET RR 1 R15C57[1][B] phy_reg_config/mdio_bit_shift/state.OP_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682 0.682 tCL RR 269 PLL_B Gowin_PLL/PLLA_inst/CLKOUT1
1.048 0.366 tNET RR 1 R15C57[1][B] phy_reg_config/mdio_bit_shift/state.OP_s0/CLK
0.860 -0.189 tHld 1 R15C57[1][B] phy_reg_config/mdio_bit_shift/state.OP_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay cell: 0.365, 27.836%; route: 0.766, 58.437%; tC2Q: 0.180, 13.727%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.499
Actual Width: 3.499
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.557 0.875 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.056 0.374 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW2

MPW Summary:

Slack: 2.499
Actual Width: 3.499
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.557 0.875 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.056 0.374 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

MPW3

MPW Summary:

Slack: 2.499
Actual Width: 3.499
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.557 0.875 tNET FF UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.056 0.374 tNET RR UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW4

MPW Summary:

Slack: 2.501
Actual Width: 3.501
Required Width: 1.000
Type: High Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
1.561 0.878 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.062 0.380 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack: 2.501
Actual Width: 3.501
Required Width: 1.000
Type: High Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
1.561 0.878 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.062 0.380 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

MPW6

MPW Summary:

Slack: 2.501
Actual Width: 3.501
Required Width: 1.000
Type: High Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
1.561 0.878 tNET RR UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.062 0.380 tNET FF UDP_Send/eth_dcfifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 2.503
Actual Width: 3.503
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.547 0.865 tNET FF controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.051 0.369 tNET RR controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW8

MPW Summary:

Slack: 2.503
Actual Width: 3.503
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.547 0.865 tNET FF controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.051 0.369 tNET RR controller_top/cache1/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB

MPW9

MPW Summary:

Slack: 2.503
Actual Width: 3.503
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.547 0.865 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.051 0.369 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB

MPW10

MPW Summary:

Slack: 2.503
Actual Width: 3.503
Required Width: 1.000
Type: Low Pulse Width
Clock: Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
Objects: controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
4.682 0.682 tCL FF Gowin_PLL/PLLA_inst/CLKOUT0
5.547 0.865 tNET FF controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.682 0.682 tCL RR Gowin_PLL/PLLA_inst/CLKOUT0
9.051 0.369 tNET RR controller_top/cache2/dc_fifo/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
395 wrclk -1.484 0.915
269 clk_50m -0.637 0.913
106 camera1_pclk_d -1.545 1.687
106 camera2_pclk_d -2.670 3.181
73 reset_r[1] 1.704 1.450
73 reset_r[1] 1.638 1.503
64 n1182_7 -0.637 2.751
56 reset_w[1] 1.979 2.441
56 reset_w[1] 2.282 1.979
52 reset_w[1] 2.092 1.247

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C42 54.17%
R15C57 51.39%
R11C41 51.39%
R26C57 47.22%
R14C53 45.83%
R15C58 45.83%
R26C42 45.83%
R20C45 45.83%
R13C53 44.44%
R11C42 44.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command