Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\Camera_ETH_Formator.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\cache.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\camera_init.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\i2c_control\i2c_bit_shift.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\i2c_control\i2c_control.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\ov2640_init_table_rgb.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\ov5640_init_table_jpeg.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\ov5640_init_table_rgb.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\camera_init\ov7725_init_table_rgb.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\controller.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\controller_top.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\controller_top_tb.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\dc_fifo\dc_fifo.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\eth\CRC32_D8.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\eth\UDP_Send.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\eth_dcfifo\eth_dcfifo.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\gmii_to_rgmii.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\gowin_pll\gowin_pll.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\mdio\mdio_bit_shift.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\mdio\mdio_tb.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\mdio\phy_reg_config.v
H:\01_gaoyun\01_gao_project\ov2640x2_udp_rgmii\src\ov2640x2_udp_rgmii.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Mon Feb 26 17:58:12 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module ov2640x2_udp_rgmii
Synthesis Process Running parser:
    CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 91.590MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 91.590MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 91.590MB
    Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.161s, Peak memory usage = 91.590MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 91.590MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 91.590MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 91.590MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 91.590MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 91.590MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 91.590MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 91.590MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 105.043MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 105.043MB
Generate output files:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 105.043MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 105.043MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 44
I/O Buf 44
    IBUF 24
    OBUF 17
    TBUF 1
    IOBUF 2
Register 844
    DFFSE 34
    DFFRE 11
    DFFPE 27
    DFFCE 772
LUT 1389
    LUT2 206
    LUT3 369
    LUT4 814
ALU 132
    ALU 132
SSRAM 4
    RAM16S4 4
INV 36
    INV 36
IOLOGIC 6
    ODDR 6
BSRAM 12
    SDPB 10
    pROM 2
CLOCK 1
    PLLA 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1581(1425 LUT, 132 ALU, 4 RAM16) / 23040 7%
Register 844 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 844 / 23685 4%
BSRAM 12 / 56 22%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
camera1_pclk Base 10.000 100.0 0.000 5.000 camera1_pclk_ibuf/I
camera2_pclk Base 10.000 100.0 0.000 5.000 camera2_pclk_ibuf/I
controller_top/cache1/dc_fifo/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 controller_top/cache1/dc_fifo/fifo_inst/n4_s2/O
controller_top/cache1/dc_fifo/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 controller_top/cache1/dc_fifo/fifo_inst/n9_s2/O
controller_top/cache2/dc_fifo/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 controller_top/cache2/dc_fifo/fifo_inst/n4_s2/O
controller_top/cache2/dc_fifo/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 controller_top/cache2/dc_fifo/fifo_inst/n9_s2/O
UDP_Send/eth_dcfifo/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 UDP_Send/eth_dcfifo/fifo_inst/n4_s2/O
UDP_Send/eth_dcfifo/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 UDP_Send/eth_dcfifo/fifo_inst/n9_s2/O
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Generated 8.000 125.0 0.000 4.000 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk Generated 20.000 50.0 0.000 10.000 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT1
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk Generated 41.600 24.0 0.000 20.800 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT2

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 camera1_pclk 100.0(MHz) 238.0(MHz) 6 TOP
2 camera2_pclk 100.0(MHz) 238.0(MHz) 6 TOP
3 controller_top/cache1/dc_fifo/fifo_inst/n4_6 100.0(MHz) 1577.9(MHz) 1 TOP
4 controller_top/cache1/dc_fifo/fifo_inst/n9_6 100.0(MHz) 1577.9(MHz) 1 TOP
5 controller_top/cache2/dc_fifo/fifo_inst/n4_6 100.0(MHz) 1577.9(MHz) 1 TOP
6 controller_top/cache2/dc_fifo/fifo_inst/n9_6 100.0(MHz) 1577.9(MHz) 1 TOP
7 UDP_Send/eth_dcfifo/fifo_inst/n4_6 100.0(MHz) 1577.9(MHz) 1 TOP
8 UDP_Send/eth_dcfifo/fifo_inst/n9_6 100.0(MHz) 1577.9(MHz) 1 TOP
9 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk 125.0(MHz) 144.0(MHz) 10 TOP
10 Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk 50.0(MHz) 222.7(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.058
Data Arrival Time 7.898
Data Required Time 8.955
From controller_top/controller/cnt_5_s2
To UDP_Send/eth_dcfifo/fifo_inst/Full_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.831 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
1.019 0.188 tNET RR 1 controller_top/controller/cnt_5_s2/CLK
1.401 0.382 tC2Q RR 4 controller_top/controller/cnt_5_s2/Q
1.589 0.188 tNET RR 1 controller_top/controller/n121_s9/I0
2.115 0.526 tINS RR 2 controller_top/controller/n121_s9/F
2.303 0.188 tNET RR 1 controller_top/controller/n121_s11/I0
2.829 0.526 tINS RR 2 controller_top/controller/n121_s11/F
3.016 0.188 tNET RR 1 controller_top/controller/fifo_wrreq_Z_s0/I2
3.478 0.461 tINS RR 9 controller_top/controller/fifo_wrreq_Z_s0/F
3.665 0.188 tNET RR 1 controller_top/controller/fifo_wrreq_Z_s/I1
4.181 0.516 tINS RR 5 controller_top/controller/fifo_wrreq_Z_s/F
4.369 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_2_s1/I1
4.885 0.516 tINS RR 15 UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_2_s1/F
5.073 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_10_s1/I1
5.589 0.516 tINS RR 7 UDP_Send/eth_dcfifo/fifo_inst/Equal.wgraynext_10_s1/F
5.777 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s15/I1
6.293 0.516 tINS RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s15/F
6.480 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s2/I0
7.007 0.526 tINS RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s2/F
7.194 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s0/I1
7.710 0.516 tINS RR 1 UDP_Send/eth_dcfifo/fifo_inst/wfull_val_s0/F
7.898 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.832 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
9.019 0.188 tNET RR 1 UDP_Send/eth_dcfifo/fifo_inst/Full_s0/CLK
8.955 -0.064 tSu 1 UDP_Send/eth_dcfifo/fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 8.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%
Arrival Data Path Delay: cell: 4.621, 67.181%; route: 1.875, 27.258%; tC2Q: 0.382, 5.561%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%

Path 2

Path Summary:
Slack 1.182
Data Arrival Time 9.589
Data Required Time 10.771
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk camera2_pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.832 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
9.019 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0/CLK
9.401 0.382 tC2Q RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_0_s0/Q
9.589 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 camera2_pclk_ibuf/I
10.682 0.683 tINS RR 105 camera2_pclk_ibuf/O
10.870 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0/CLK
10.835 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
10.771 -0.064 tSu 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_0_s0
Path Statistics:
Clock Skew: -0.149
Setup Relationship: 2.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.188, 32.895%; tC2Q: 0.382, 67.105%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%

Path 3

Path Summary:
Slack 1.182
Data Arrival Time 9.589
Data Required Time 10.771
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk camera2_pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.832 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
9.019 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0/CLK
9.401 0.382 tC2Q RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_1_s0/Q
9.589 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 camera2_pclk_ibuf/I
10.682 0.683 tINS RR 105 camera2_pclk_ibuf/O
10.870 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0/CLK
10.835 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
10.771 -0.064 tSu 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_1_s0
Path Statistics:
Clock Skew: -0.149
Setup Relationship: 2.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.188, 32.895%; tC2Q: 0.382, 67.105%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%

Path 4

Path Summary:
Slack 1.182
Data Arrival Time 9.589
Data Required Time 10.771
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk camera2_pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.832 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
9.019 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0/CLK
9.401 0.382 tC2Q RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_2_s0/Q
9.589 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 camera2_pclk_ibuf/I
10.682 0.683 tINS RR 105 camera2_pclk_ibuf/O
10.870 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0/CLK
10.835 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
10.771 -0.064 tSu 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_2_s0
Path Statistics:
Clock Skew: -0.149
Setup Relationship: 2.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.188, 32.895%; tC2Q: 0.382, 67.105%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%

Path 5

Path Summary:
Slack 1.182
Data Arrival Time 9.589
Data Required Time 10.771
From controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0
To controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
Launch Clk Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk camera2_pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
8.000 0.000 Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
8.832 0.831 tCL RR 391 Gowin_PLL/PLLA_inst/CLKOUT0
9.019 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0/CLK
9.401 0.382 tC2Q RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.rptr_3_s0/Q
9.589 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 camera2_pclk
10.000 0.000 tCL RR 1 camera2_pclk_ibuf/I
10.682 0.683 tINS RR 105 camera2_pclk_ibuf/O
10.870 0.188 tNET RR 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0/CLK
10.835 -0.035 tUnc controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
10.771 -0.064 tSu 1 controller_top/cache2/dc_fifo/fifo_inst/Equal.wq1_rptr_3_s0
Path Statistics:
Clock Skew: -0.149
Setup Relationship: 2.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.188, 32.895%; tC2Q: 0.382, 67.105%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.188, 100.000%