| File | Description |
|---|
| ddr22.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| ddr22_bb.v | Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design. |
| ddr22.bsf | Quartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. |
| ddr22.qip | Contains Quartus II project information for your MegaCore function variation. |
| ddr22.html | The MegaCore function report file. |
| ddr22_example_driver.v | Example self-checking test generator that matches your variation. |
| ddr22_example_top.v | Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller. |
| ddr22_example_top.sdc | Example Synopsys Design Constraints file for paths in the example top level. |
| ddr22_ex_lfsr8.v | Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver. |
| testbench | ddr22_example_top_tb.v | Example testbench that instantiates the example top level design file and the example memory model. |
| testbench | ddr22_mem_model.v | A simple example memory model that matches your variation. |
| testbench | ddr22_full_mem_model.v | Memory model that allocates memory for all available addresses. |
| ddr22_pin_assignments.tcl | TCL script |
| ddr22_advisor.ipa | IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software. |
| ddr22_phy.qip | Generated ALTMEMPHY QIP file. |