Generation Report - DDR2 SDRAM Controller with ALTMEMPHY v13.0

Entity Nameddr22_controller_phy
Variation Nameddr22
Variation HDLVerilog HDL
Output DirectoryE:\fpgatmp\DDR2_Sim

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
ddr22.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr22_bb.vVerilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
ddr22.bsfQuartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
ddr22.qipContains Quartus II project information for your MegaCore function variation.
ddr22.htmlThe MegaCore function report file.
ddr22_example_driver.vExample self-checking test generator that matches your variation.
ddr22_example_top.vExample top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller.
ddr22_example_top.sdcExample Synopsys Design Constraints file for paths in the example top level.
ddr22_ex_lfsr8.vExample linear feedback shift register that is used to generate the pseudo-random test data for the example driver.
testbench | ddr22_example_top_tb.vExample testbench that instantiates the example top level design file and the example memory model.
testbench | ddr22_mem_model.vA simple example memory model that matches your variation.
testbench | ddr22_full_mem_model.vMemory model that allocates memory for all available addresses.
ddr22_pin_assignments.tclTCL script
ddr22_advisor.ipaIP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software.
ddr22_phy.qipGenerated ALTMEMPHY QIP file.

MegaCore Function Variation File Ports

NameDirectionWidth
local_addressINPUT24
local_write_reqINPUT1
local_read_reqINPUT1
local_burstbeginINPUT1
local_readyOUTPUT1
local_rdataOUTPUT32
local_rdata_validOUTPUT1
local_wdataINPUT32
local_beINPUT4
local_sizeINPUT3
local_refresh_ackOUTPUT1
local_init_doneOUTPUT1
reset_phy_clk_nOUTPUT1
mem_odtOUTPUT1
mem_clkBIDIR1
mem_clk_nBIDIR1
mem_cs_nOUTPUT1
mem_ckeOUTPUT1
mem_addrOUTPUT13
mem_baOUTPUT2
mem_ras_nOUTPUT1
mem_cas_nOUTPUT1
mem_we_nOUTPUT1
mem_dqBIDIR16
mem_dqsBIDIR2
mem_dmOUTPUT2
global_reset_nINPUT1
pll_ref_clkINPUT1
phy_clkOUTPUT1
aux_full_rate_clkOUTPUT1
aux_half_rate_clkOUTPUT1
soft_reset_nINPUT1
reset_request_nOUTPUT1