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【疑问解答】数码管实验全编译报时钟警告

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  • TA的每日心情
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    2019-5-10 10:58
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    发表于 2019-1-13 14:59:01 | 显示全部楼层 |阅读模式
    Warning (12010): Port "probe" on the entity instantiation of "altsource_probe_component" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be driven by GND.
    Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
    Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
    Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
    22222222222222.png

    解决方案:
    新建一个SDC格式的文件,将下述内容复制粘贴到文件中,然后将该文件保存为HEX_top.sdc,然后添加到工程中,再编译就可以了。

    1. #**************************************************************
    2. # Time Information
    3. #**************************************************************

    4. set_time_format -unit ns -decimal_places 3



    5. #**************************************************************
    6. # Create Clock
    7. #**************************************************************

    8. create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
    9. create_clock -name {Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {Clk}]


    10. #**************************************************************
    11. # Create Generated Clock
    12. #**************************************************************

    13. create_generated_clock -name {clk1k} -source [get_ports {Clk}] -divide_by 50000 -master_clock {Clk} [get_registers {HEX8:HEX8|clk_1K}]


    14. #**************************************************************
    15. # Set Clock Latency
    16. #**************************************************************



    17. #**************************************************************
    18. # Set Clock Uncertainty
    19. #**************************************************************
    20. derive_clock_uncertainty


    21. #**************************************************************
    22. # Set Input Delay
    23. #**************************************************************



    24. #**************************************************************
    25. # Set Output Delay
    26. #**************************************************************



    27. #**************************************************************
    28. # Set Clock Groups
    29. #**************************************************************

    30. set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
    31. set_clock_groups -asynchronous -group [get_clocks {Clk clk1k}]

    复制代码


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  • TA的每日心情
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     楼主| 发表于 2019-1-13 15:00:23 | 显示全部楼层
    如需了解更多,敬请关注小梅哥的后续时序约束的系列教程。(正在认真筹备中)
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